bbt3821 Intersil Corporation, bbt3821 Datasheet - Page 55

• Manufacturer Part Number: bbt3821
• Description: Octal Multi-rate Lx4/cx4 - Xaui Re-timer
• Manufacturer: Intersil Corporation

Pin Specifications
T9/T8
C10
T14/T15
P14/P15
M14/M15
K14/K15
H14/H15
F14/F15
D14/D15
B14/B15
A2/A3
C2/C3
E2/E3
G2/G3
R2/R3
N2/N3
L2/L3
J2/J3
D12
B12
D8
C12
C8
PIN#
PIN#
PIN#
PIN#
RFCP/RFCN
TXCLK20
TXP0P/TXP0N
TXP1P/TXP1N
TXP2P/TXP2N
TXP3P/TXP3N
RXP0P/RXP0N
RXP1P/RXP1N
RXP2P/RXP2N
RXP3P/RXP3N
TCX0P/TCX0N
TCX1P/TCX1N
TCX2P/TCX2N
TCX3P/TCX3N
RCX0P/RCX0N
RCX1P/RCX1N
RCX2P/RCX2N
TDI
TDO
TMS
TCLK
TRSTN
RCX3P/RCX3N
NAME
NAME
NAME
NAME
55
Input (with pullup)
Output (open drain)
Input (with pullup)
Input (with pulldown)
Input (with pullup)
Table 95. XAUI (XENPAK/XPAK/X2) SIDE SERIAL DATA PINS
Input
LVPECL
Output
1.5V CMOS
Output CML
Input CML
Output CML
Input CML
Table 96. PMA/PMD (CX4/LX4) SIDE SERIAL DATA PINS
TYPE
TYPE
TYPE
TYPE
Table 97. JTAG INTERFACE PINS
Differential Reference Input Clock. The reference input clock frequency is line rate
clock frequency divided by 20 (full rate mode) or 10 (half rate mode). The pins are
internally biased at VDDA/2, and should be AC coupled.
Transmit Clock Output. Divided-by-20 transmit clock output.
Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
Table 94. CLOCK PINS
BBT3821
JTAG Input Data. 1.5V CMOS
JTAG Output Data. 1.5V CMOS, 2.5V Tolerant
JTAG Mode Select. 1.5V CMOS
JTAG Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
JTAG Reset. 1.5V CMOS
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION