pcf8564a NXP Semiconductors, pcf8564a Datasheet - Page 21

• Manufacturer Part Number: pcf8564a
• Description: Real Time Clock And Calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
9. Characteristics of the I
PCF8564A_1
Product data sheet
9.1 Bit transfer
9.2 START and STOP conditions
9.3 System configuration
The I
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP
condition (P), see
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see
Fig 12. Bit transfer
Fig 13. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 1 — 8 October 2009
13.
data valid
data line
stable;
Figure
Figure
change
allowed
of data
12).
14).
Real time clock and calendar
STOP condition
mbc621
PCF8564A
P
© NXP B.V. 2009. All rights reserved.
mbc622
SDA
SCL
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