adc14155wrqv National Semiconductor Corporation, adc14155wrqv Datasheet - Page 20

• Manufacturer Part Number: adc14155wrqv
• Description: Adc14155qml 14-bit, 155 Msps, 1.1 Ghz Bandwidth A/d Converter
• Manufacturer: National Semiconductor Corporation

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ground plane at a single, quiet point to minimize the effects of
noise currents in the ground path.
The Reference Bypass Pins (V
available for bypass purposes. All these pins should each be
bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a
10 µF capacitor should be placed between the V
pins, as shown in
avoid reference oscillation, which could result in reduced SF-
DR and/or SNR. V
temperature stable 1.5V reference. The remaining pins
should not be loaded.
Smaller capacitor values than those specified will allow faster
recovery from the power down mode, but may result in de-
graded noise performance. Loading any of these pins, other
than V
The nominal voltages for the reference bypass pins are as
follows:
4.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK+, CLK−, PD
and CLK_SEL/DF.
4.1 Clock Inputs
The CLK+ and CLK− signals control the timing of the sampling
process. The CLK_SEL/DF pin (pin 8) allows the user to con-
figure the ADC for either differential or single-ended clock
mode (see Section 3.3). In differential clock mode, the two
clock signals should be exactly 180° out of phase from each
other and of the same amplitude. In the single-ended clock
mode, the clock signal should be routed to the CLK+ input and
the CLK− input should be tied to AGND in combination with
the correct setting from
To achieve the optimum noise performance, the clock inputs
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
through a high speed buffer gate. This configuration is shown
in
short as possible and should not cross any other signal line,
analog or digital, not even at 90°.
mended clock input circuit.
The clock signal also drives an internal state machine. If the
clock is interrupted, or its frequency is too low, the charge on
the internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC clock
pins only drive that pin. However, if that source is used to drive
other devices, then each driven pin should be AC terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and the
capacitor value is
V
V
V
Figure
RM
RP
RN
RM
= V
= V
= 1.5 V
, may result in performance degradation.
4. The trace carrying the clock signal should be as
RM
RM
+ V
− V
REF
REF
Figure
RM
/ 2
/ 2
may be loaded to 1mA for use as a
Table
4. This configuration is necessary to
3.
RP
Figure 4
, V
RM
, and V
shows the recom-
RN
) are made
RP
and V
RN
20
where t
"L" is the line length and Z
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t
board material. The units of "L" and t
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC14155 has a Duty Cycle Stabilizer. It is
designed to maintain performance over a clock duty cycle
range of 30% to 70%.
4.2 Power-Down (PD)
Power-down can be enabled through this two-state input pin.
Table 2
The power-down mode allows the user to conserve power
when the converter is not being used. In the power-down state
all bias currents of the analog circuitry, excluding the refer-
ence are shut down which reduces the power consumption to
5 mW with no clock running. The output data pins are unde-
fined and the data in the pipeline is corrupted while in the
power-down mode.
The Power-down Mode Exit Cycle time is determined by the
value of the capacitors on the V
47) and V
and 45) and is about 3 ms with the recommended component
values. These capacitors lose their charge in the power-down
mode and must be recharged by on-chip circuitry before con-
versions can be accurate. Smaller capacitor values allow
slightly faster recovery from the power down mode, but can
result in a reduction in SNR, SINAD and ENOB performance.
4.3 Clock Mode Select/Data Format (CLK_SEL/DF)
Single-ended versus differential clock mode and output data
format are selectable using this quad-state function pin.
3
put data formats.
5.0 DIGITAL OUTPUTS
Digital outputs consist of the 1.8V CMOS signals D0-D13,
DRDY and OVR.
The ADC14155 has 16 CMOS compatible data output pins:
14 data output bits corresponding to the converted input val-
ue, a data ready (DRDY) signal that should be used to capture
the output data and an over-range indicator (OVR) which is
set high when the sample amplitude exceeds the 14-bit con-
version range. Valid data is present at these outputs while the
PD pin is low.
TABLE 3. Clock Mode and Data Format Selection Table
shows how to select between the clock modes and the out-
Input Voltage
CLK_SEL/DF
(2/3) * V
(1/3) * V
PD
AGND
shows how to power-down the ADC14155.
TABLE 2. Power Down Selection Table
V
RN
is the signal propagation rate down the clock line,
A
PD Input Voltage
(pin 44, 45) reference bypass pins (pins 43, 44
A
A
PD
AGND
V
is about 150 ps/inch (60 ps/cm) on FR-4
A
Single-Ended
Single-Ended
Clock Mode
Differential
Differential
O
is the characteristic impedance
RP
Power State
Power-down
(pin 42, 43), V
PD
On
should be the same
2's Complement
2's Complement
Offset Binary
Offset Binary
Output Data
Format
RM
(pin 46,
Table