adc14155wrqv National Semiconductor Corporation, adc14155wrqv Datasheet - Page 3

• Manufacturer Part Number: adc14155wrqv
• Description: Adc14155qml 14-bit, 155 Msps, 1.1 Ghz Bandwidth A/d Converter
• Manufacturer: National Semiconductor Corporation

ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
42, 43
46, 47
44, 45
48
11
12
4
5
Symbol
CLK+
CLK−
V
V
V
V
V
V
REF
IN
IN
RM
RN
RP
−
+
Equivalent Circuit
3
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, V
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V
and a 10 µF capacitor should be placed in parallel.
V
use as a temperature stable 1.5V reference.
It is recommended to use V
voltage, V
This pin can be used as either the +1.0V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, V
with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In
this mode, V
reference.
To use an external reference, overdrive this pin with a low noise
external reference voltage. The output impedance of the internal
reference at this pin is 9kΩ. Therefore, to overdrive this pin, the
impedance of the external reference source should be << 9kΩ.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * V
The clock input pins can be configured to accept either a single-
ended or a differential clock input signal.
When the single-ended clock mode is selected through CLK_SEL/
DF (pin 8), connect the clock input signal to the CLK+ pin and
connect the CLK− pin to AGND.
When the differential clock mode is selected through CLK_SEL/DF
(pin 8), connect the positive and negative clock inputs to the CLK
+ and CLK− pins, respectively.
The analog input is sampled on the falling edge of the clock input.
RP
and V
CM
RN
, for the differential analog inputs, V
REF
should not be loaded. V
defaults as the output for the internal 1.0V
RP
and V
Description
RM
RN
to provide the common mode
REF
as close to the pins as possible,
should be decoupled to AGND
RM
may be loaded to 1mA for
CM
.
IN
+ and V
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REF
.
IN
−.