adc14155wrqv National Semiconductor Corporation, adc14155wrqv Datasheet - Page 4

• Manufacturer Part Number: adc14155wrqv
• Description: Adc14155qml 14-bit, 155 Msps, 1.1 Ghz Bandwidth A/d Converter
• Manufacturer: National Semiconductor Corporation

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ANALOG POWER
1, 3, 6, 10, 38,
DIGITAL POWER
16, 25, 26, 36
2, 9, 37, 40,
Pin No.
17-24,
15, 35
27-32
33
34
41
39
13
14
8
7
CLK_SEL/DF
Symbol
D0–D13
DRGND
DGND
DRDY
AGND
OVR
V
PD
V
V
DR
A
D
Equivalent Circuit
4
This is a four-state pin controlling the input clock mode and output
data format.
CLK_SEL/DF = V
differential clock input. The output data format is 2's complement.
CLK_SEL/DF = (2/3)*V
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*V
clock input and CLK− should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK− should be tied to AGND. The output data format is
offset binary.
This is a two-state input controlling Power Down.
PD = V
the reference voltage circuitry remains active and power
dissipation is reduced.
PD = AGND, Normal operation.
Digital data output pins that make up the 14-bit conversion result.
D0 (pin 17) is the LSB, while D13 (pin 32) is the MSB of the output
word. Output levels are CMOS compatible.
Over-Range Indicator. This output is set HIGH when the input
amplitude exceeds the 14-bit conversion range (0 to 16383).
Data Ready Strobe. This pin is used to clock the output data. It has
the same frequency as the sampling clock. One word of data is
output in each cycle of this signal. The rising edge of this signal
should be used to capture the output data.
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and be bypassed to AGND with 100 pF and 0.1
µF capacitors located close to the power pins.
The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to a quiet
+3.3V source and be bypassed to DGND with a 100 pF and 0.1 µF
capacitor located close to the power pin.
The ground return for the digital supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source of +1.8V and be bypassed to
DRGND with 100 pF and 0.1 µF capacitors located close to the
power pins.
The ground return for the digital output driver supply. These pins
should be connected to the system digital ground. See Section 7.0
(Layout and Grounding) for more details.
A
, Power Down is enabled. In the Power Down state only
A
, CLK+ and CLK− are configured as a
A
A
, CLK+ and CLK− are configured as a
, CLK+ is configured as a single-ended
Description