kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 16

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

Theory of Operation
Functional Description
The KAD5512P is based upon a 12-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 23). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted to
a unit of charge. Proprietary charge-domain techniques are
used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of seven and one half clock cycles.
This is evident to the user as a time lag between the start of a
conversion and the data being available on the digital outputs.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage
ramps and initiates the calibration when the analog and
digital supply voltages are above a threshold. The following
conditions must be adhered to for the power-on calibration to
execute successfully:
• A frequency-stable conversion clock must be applied to
• DNC pins (especially 3, 4 and 18) must not be pulled up or
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
the CLKP/CLKN pins
down
INN
INP
1.25V
16
SHA
+
–
FIGURE 23. ADC CORE BLOCK DIAGRAM
2.5-BIT
FLASH
KAD5512P
1.5-BIT/STAGE
6-STAGE
A user-initiated reset can subsequently be invoked in the
event that the previously mentioned conditions cannot be
met at power-up.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized, the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent user-initiated
reset is required, the RESETN pin should be connected to an
open-drain driver with a drive strength of less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 24. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition, the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
LVDS/LVCMOS
GENERATION
CORRECTION
OUTPUTS
DIGITAL
CLOCK
ERROR
1-BIT/STAGE
3-STAGE
FLASH
3-BIT
January 16, 2009
FN6807.1