kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 19

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

A delay-locked loop (DLL) generates internal clock signals
for various stages within the charge pipeline. If the frequency
of the input clock changes, the DLL may take up to 52µs to
regain lock at 250MSPS. The lock time is inversely
proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t
is illustrated in Figure 32.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1. The internal aperture jitter combines with the input
clock jitter in a root-sum-square fashion, since they are not
statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise
sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional
to the reference voltage. The voltage reference is internally
bypassed and is not accessible to the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or single
data rate (SDR) formats. The even numbered output bits are
active in DDR mode. When CLKOUT is low the MSB and all
odd bits are output, while on the high phase the LSB and all
even bits are presented. Figures 1 and 2 show the timing
relationships for LVDS/CMOS and DDR/SDR modes.
SNR
100
95
90
85
80
75
70
65
60
55
50
1
=
20 log
FIGURE 32. SNR vs CLOCK JITTER
tj = 100ps
10
⎛
⎝
------------------- -
2πf
1
IN
INPUT FREQUENCY (MHz)
J
t
) and SNR is shown in Equation 1 and
10
J
⎞
⎠
tj = 10ps
19
tj = 1ps
tj = 0.1ps
100
10 BITS
14 BITS
12 BITS
(EQ. 1)
1000
KAD5512P
The 48-QFN package option contains six LVDS data
outputs, and therefore can only support DDR mode.
Additionally, the drive current for LVDS mode can be set to a
nominal 3 mA or a power-saving 2 mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the ADC. The applicability of this setting
is dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 22.
An external resistor creates the bias for the LVDS drivers. A
10kΩ, 1% resistor must be connected from the RLVDS pin to
OVSS.
Over Range Indicator
The over range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode).
The output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5512P is primarily
dependent on the sample rate and the output modes: LVDS
vs. CMOS and DDR vs. SDR. There is a static bias in the
analog supply, while the remaining power dissipation is
linearly related to the sample rate. The output supply
dissipation is approximately constant in LVDS mode, but
linearly related to the clock frequency in CMOS mode.
Figures 36 and 37 illustrate these relationships.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required. Two
power saving modes are available: nap, and sleep. Nap
mode is only available through SPI control, while Sleep
mode can be selected with the pin or through SPI.
Nap mode reduces power dissipation by approximately 70%
(depending on operating state) and recovers to normal
operation in approximately 1µs. Sleep mode reduces power
dissipation to less than 20mW but requires 1ms to recover.
The clock should remain running and at a fixed frequency
during Nap or Sleep. Recovery time from Nap mode will
OUTMODE PIN
AVDD
AVSS
Float
TABLE 2. OUTMODE PIN SETTINGS
LVDS, 3mA
LVDS, 2mA
LVCMOS
MODE
January 16, 2009
FN6807.1