kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 8

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

Switching Specifications
NOTES:
10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
Latency (Pipeline Delay)
Over Voltage Recovery
SPI INTERFACE (Notes 7, 8)
SCLK Period
SCLK Duty Cycle (t
SCLK↑ to CSB↓ Setup Time
SCLK↑ to CSB↑ Hold Time
SCLK↑ to Data Setup Time
SCLK↑ to Data Hold Time
7. SPI Interface timing is directly proportional to the ADC sample period (t
8. The SPI may operate asynchronously with respect to the ADC sample clock.
9. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
scaled proportionally for lower sample rates.
depending on desired function.
applications. Contact factory for more info if needed.
PARAMETER
HI
/t
CLK
or t
LO
8
/t
CLK)
(Continued)
Write Operation
Read Operation
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
CONDITION
KAD5512P
S
). Values above reflect multiples of a 4ns sample period, and must be
SYMBOL
t
t
t
OVR
t
CLK
CLK
t
DH
t
t
DS
L
S
H
MIN
264
-12
-12
64
25
-4
-4
TYP
7.5
50
1
MAX
75
January 16, 2009
UNITS
cycles
cycles
ns
ns
ns
ns
ns
ns
%
FN6807.1