kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 24

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

SLIP TWICE
SLIP ONCE
Nap mode must be entered by executing the following
sequence:
Return to Normal operation as follows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle when in CLK/4 mode, as
shown in Figure 40. Execution of a phase_slip command is
accomplished by first writing a ‘0’ to bit 0 at address 71h
followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles ).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 18). This functionality can be overridden and
CLK÷4
CLK÷4
CLK÷4
FIGURE 40. PHASE SLIP: CLK÷4 MODE, f
CLK
SEQUENCE
SEQUENCE
1
2
3
4
1
2
3
4
CLK = CLKP – CLKN
REGISTER
REGISTER
1.00ns
0x10
0x25
0x10
0x25
0x10
0x25
0x10
0x25
24
4.00ns
CLOCK
VALUE
VALUE
0x01
0x02
0x02
0x02
0x01
0x01
0x02
0x01
= 1000MHz
KAD5512P
controlled through the SPI, as shown in Table 11. This
register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P can present output data in two physical formats:
LVDS or LVCMOS. Additionally, the drive strength in LVDS
mode can be set high (3mA) or low (2mA). By default, the
tri-level OUTMODE pin selects the mode and drive level
(refer to “Digital Outputs” on page 19). This functionality can
be overridden and controlled through the SPI, as shown in
Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 20). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
TABLE 11. CLOCK DIVIDER SELECTION
TABLE 13. OUTPUT FORMAT CONTROL
VALUE
VALUE
TABLE 12. OUTPUT MODE CONTROL
VALUE
000
001
010
100
000
001
010
100
000
001
010
100
OUTPUT FORMAT
Two’s Complement
CLOCK DIVIDER
Offset Binary
Pin Control
Divide by 1
Divide by 2
Divide by 4
Pin Control
Gray Code
0x72[2:0]
0x93[2:0]
Pin Control
LVDS 2mA
LVDS 3mA
0x93[7:5]
LVCMOS
January 16, 2009
FN6807.1