kad5512p-21q72ep-i Intersil Corporation, kad5512p-21q72ep-i Datasheet - Page 7

• Manufacturer Part Number: kad5512p-21q72ep-i
• Description: Low Power 12-bit, 250/210/170/125msps Adc
• Manufacturer: Intersil Corporation

D[10/8/6/4/2/0]P
D[10/8/6/4/2/0]N
D[10/8/6/4/2/0]
Timing Diagrams
Switching Specifications
ADC OUTPUT
Aperture Delay
RMS Aperture Jitter
Output Clock to Data Propagation Delay,
LVDS Mode
(Note 10)
Output Clock to Data Propagation Delay,
CMOS Mode
(Note 10)
CLKOUTN
CLKOUTP
CLKOUT
CLKP
CLKN
CLKN
CLKP
INP
INN
INP
INN
t
t
CPD
CPD
t
PARAMETER
SAMPLE N
A
SAMPLE N
t
A
ODD BITS
ODD BITS
N-L
N-L
EVEN BITS
t
t
EVEN BITS
PD
FIGURE 1A. DDR
FIGURE 2A. DDR
PD
N-L
t
N-L
DC
t
DC
LATENCY = L CYCLES
ODD BITS
LATENCY = L CYCLES
N-L + 1
ODD BITS
N-L + 1
7
EVEN BITS
EVEN BITS
N-L + 1
N-L + 1
ODD BITS
N-L + 2
ODD BITS
N-L + 2
DDR Rising Edge
DDR Falling Edge
SDR Falling Edge
DDR Rising Edge
DDR Falling Edge
SDR Falling Edge
EVEN BITS
EVEN BITS
N-L + 2
N-L + 2
FIGURE 1. LVDS TIMING DIAGRAMS
FIGURE 2. CMOS TIMING DIAGRAM
CONDITION
ODD BITS
ODD BITS
N
N
KAD5512P
CLKOUT
CLKOUTN
SYMBOL
CLKOUTP
D[11/0]
CLKP
CLKN
D[11/0]P
D[11/0]N
t
t
t
t
t
t
INP
INN
DC
DC
DC
DC
DC
DC
t
j
CLKN
CLKP
A
A
INP
INN
t
CPD
t
CPD
t
SAMPLE N
A
SAMPLE N
t
A
-260
-160
-260
-220
-310
-310
MIN
FIGURE 1B. SDR
FIGURE 2B. SDR
t
PD
LATENCY = L CYCLES
t
LATENCY = L CYCLES
PD
t
DC
t
DC
DATA
TYP
375
N-L
DATA
-50
-40
-10
-90
-50
60
10
N-L
N-L + 1
N-L + 1
DATA
DATA
MAX
120
230
230
200
200
110
January 16, 2009
UNITS
ps
ps
ps
ps
ps
ps
ps
fs
FN6807.1
DATA
N
DATA
N