lm12l458civf National Semiconductor Corporation, lm12l458civf Datasheet - Page 18

• Manufacturer Part Number: lm12l458civf
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

www.national.com
1.0 Functional Description
The LM12L458 is a multi-functional Data Acquisition System
that includes a fully differential 12-bit-plus-sign self-
calibrating analog-to-digital converter (ADC) with a two’s-
complement output format, an 8-channel analog multiplexer,
a first-in-first-out (FIFO) register that can store 32 conversion
results, and an Instruction RAM that can store as many as
eight instructions to be sequentially executed. All of this
circuitry operates on only a single +3.3V power supply.
The LM12L458 has three modes of operation:
The fully differential 12-bit-plus-sign ADC uses a charge
redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is used
by a successive approximation register to generate interme-
diate voltages between the voltages applied to V
V
the sampled analog input voltage as each bit is generated.
The number of intermediate voltages and comparisons
equals the ADC’s resolution. The correction of each bit’s
accuracy is accomplished by calibrating the capacitor ladder
used in the ADC.
Two different calibration modes are available; one compen-
sates for offset voltage, or zero error, while the other corrects
both offset error and the ADC’s linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, aver-
aged, and a correction coefficient is created. After comple-
tion of either calibration mode, the offset correction coeffi-
cient is stored in an internal offset correction register.
The LM12L458’s overall linearity correction is achieved by
correcting the internal DAC’s capacitor mismatch. Each ca-
pacitor is compared eight times against all remaining smaller
value capacitors and any errors are averaged. A correction
coefficient is then created and stored in one of the thirteen
internal linearity correction registers. An internal state ma-
chine, using patterns stored in an internal 16 x 8-bit ROM,
executes each calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction
coefficients to reduce the conversion’s offset error and lin-
earity error, in the background, during the 12-bit + sign
conversion. The 8-bit + sign conversion and comparison
modes use only the offset coefficient. The 8-bit + sign mode
performs a conversion in less than half the time used by the
12-bit + sign conversion mode.
The LM12L458’s “watchdog” mode is used to monitor a
single-ended or differential signal’s amplitude. Each
sampled signal has two limits. An interrupt can be generated
if the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are “inside the window” or, alternatively, “outside the
window”. After a “watchdog” mode interrupt, the processor
can then request a conversion on the input signal and read
the signal’s magnitude.
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel
REF+
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode (“watchdog” mode)
. These intermediate voltages are compared against
REF−
and
18
operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels
together.
The LM12L458’s internal S/H is designed to operate at its
minimum acquisition time (1.5 µs, 12 bits) when the source
impedance, R
5.56 kΩ, the internal S/H’s acquisition time can be increased
to a maximum of 6.5 µs (12 bits, f
2.1 (Instruction RAM “00”) Bits 12–15 for more information.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at any
time, interrogate the FIFO and retrieve its contents. It can
also wait for the LM12L458 to issue an interrupt when the
FIFO is full or after any number (≤32) of conversions have
been stored.
Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12L458’s operation. This mode internally connects the
voltages present at the V
internal V
setting the Diagnostic bit (Bit 11) in the Configuration register
to a “1”. More information concerning this mode of operation
can be found in Section 2.2.
2.0 Internal User-Programmable
Registers
2.1 INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit “RAM pointer” in the Configuration register. The
eight instructions are located at addresses 0000 through
0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or
at addresses 00000 through 01111 (A4–A0, BW = 1) when
using an 8-bit wide data bus. They can be accessed and
programmed in random order.
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation:
The Sequencer should be stopped by setting the RESET bit
to a “1” or by resetting the START bit in the Configuration
Register and waiting for the current instruction to finish ex-
ecution before any Instruction RAM READ or WRITE is
initiated. Bit 0 of the Configuration Register indicates the
Sequencer Status. See paragraph 2.2 for information on the
Configuration Register.
A soft RESET should be issued by writing a “1” to the
Configuration Register’s RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit “RAM Pointer”, bits D8 and
D9. The first 16-bit Instruction RAM section is selected with
the RAM Pointer equal to “00”. This section provides multi-
plexer channel selection, as well as resolution, acquisition
time, etc. The second 16-bit section holds “watchdog” limit
#1, its sign, and an indicator that shows that an interrupt can
be generated if the input signal is greater or less than the
programmed limit. The third 16-bit section holds “watchdog”
IN+
and V
S
, is ≤ 80Ω (f
IN−
S/H inputs. This mode is activated by
REF+
CLK
, V
≤ 6 MHz). When 80Ω
REF−
CLK
= 6 MHz). See Section
, and GND pins to the
<
R
S
≤