lm12l458civf National Semiconductor Corporation, lm12l458civf Datasheet - Page 25

• Manufacturer Part Number: lm12l458civf
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

3.0 Other Registers and Functions
conversion result from the FIFO. Therefore, the DMA con-
troller must be able to repeatedly access two constant ad-
dresses when transferring data from the LM12L458 to the
host system.
4.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
(A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold
either the sign bit, extending the register’s two’s complement
data format to a full sixteen bits or the instruction address
that generated the conversion and the resulting data. These
modes are selected according to the logic state of the Con-
figuration register’s Bit 5.
The FIFO status should be read in the Interrupt Status
register (Bits 11–15) to determine the number of conversion
results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12L458’s interrupt capability be used to inform the system
controller that the FIFO is full.
The lower portion (A0 = 0) of the data word (Bits 0–7) should
be read first followed by a read of the upper portion (A0 = 1)
when using the 8-bit bus width (BW = 1). Reading the upper
portion first causes the data to shift down, which results in
loss of the lower byte.
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will
be 1110 (LSB) when using 8-bit plus sign resolution.
Bits 13–15 hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable registers’s Bits 11–15 to 1111
and the Interrupt Enable register’s Bit 2 to a “1”. This gener-
ates an external interrupt when the 31st conversion is stored
in the FIFO. This gives the host processor a chance to send
a “0” to the LM12L458’s Start bit (Configuration register) and
halt the ADC before it completes the 32nd conversion. The
Sequencer halts after the current (32) conversion is com-
pleted. The conversion data is then transferred to the FIFO
and occupies the 32nd location. FIFO overflow is avoided if
the Sequencer is halted before the start of the 32nd conver-
sion by placing a “0” in the Start bit (Configuration register).
It is important to remember that the Sequencer continues to
operate even if a FIFO interrupt (INT 2) is internally or
externally generated. The only mechanisms that stop the
Sequencer are an instruction with the PAUSE bit set to “1”
(halts before instruction execution), placing a “0” in the Con-
figuration register’s START bit, or placing a “1” in the Con-
figuration register’s RESET bit.
(Continued)
25
5.0 Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 1) to retrieve the programmable conversion
instructions stored in the Instruction RAM. The 3-bit counter
is reset to 000 during chip reset or if the current executed
instruction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently
executed instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and
execution begins again with the first instruction. If all instruc-
tions have their Loop bit reset to “0”, the Sequencer will
execute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The
Sequencer can go through eight states during instruction
execution:
the Instruction RAM “00”. This state is one clock cycle long.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
figuration register is set to a “1”, state 2 is 76 clock cycles
long. If the Configuration register’s bit 3 is set to a “1”, state
2 is 4944 clock cycles long.
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
where 0 ≤ T ≤ 2
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
cycles long.
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
State 0: The current instruction’s first 16 bits are read from
State 1: Checks the state of the Calibration and Start bits.
State 2: Perform calibration. If bit 2 or bit 6 of the Con-
State 3: Run the internal 16-bit Timer. The number of
State 7: Run the acquisition delay and read Limit #1’s
State 6: Perform first comparison. This state is 5 clock
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison. This
16
−1.
32T + 2
9 + 2D
2 + 2D
www.national.com