lm12l458civf National Semiconductor Corporation, lm12l458civf Datasheet - Page 21

• Manufacturer Part Number: lm12l458civf
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or “watchdog” compari-
sons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12–15. Thus, the S/H’s acquisition
time is (9 + 2D) clock cycles for 12-bit + sign conversions
and (2 + 2D) clock cycles for 8-bit + sign conversions or
“watchdog” comparisons, where D is the value stored in Bits
12–15. The minimum acquisition time compensates for the
typical internal multiplexer series resistance of 2 kΩ, and any
additional delay created by Bits 12–15 compensates for
source resistances greater than 80Ω. (For this acquisition
A4 A3 A2 A1 A0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0
1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
to
to
to
to
to
to
FIGURE 14. LM12L458 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
0
1
0
1
0
1
(RAM Pointer = 00)
(RAM Pointer = 01)
(RAM Pointer = 10)
Instruction RAM
Instruction RAM
Instruction RAM
Interrupt Enable
Interrupt Status
Configuration
Limit Status
Conversion
Purpose
Register
Register
Register
Register
Register
Timer
FIFO
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
I/O Sel
INST7
INT7
Number of Conversions in Conversion FIFO to
D7
Actual Number of Conversions Results in
Address or Sign
Zero
Acquisition Time
Don’t
Care
Auto
V
D6
“0”
IN−
Don’t Care
21
ec
Conversion FIFO
Generate INT2
time discussion, numbers in ( ) are shown for the LM12L458
operating at 6 MHz.) The necessary acquisition time is de-
termined by the source impedance at the multiplexer input. If
the source resistance (R
6 MHz, the value stored in bits 12–15 (D) can be 0000. If R
should be stored in bits 12–15.
for 12-bits + sign
for 8-bits + sign and “watchdog”
>
INST5
Chan
Mask
80Ω, the following equations determine the value that
INT5
D5
Don’t Care
Don’t Care
Timer Preset: High Byte
Timer Preset: Low Byte
Conversion Data: LSBs
Comparison Limit #1
Comparison Limit #2
Limit #1 Status
Limit #2 Status
Stand-
INST4
INT4
Sign
D4
by
D = 0.45 x R
D = 0.36 x R
Full Cal
Watch-
INST3
V
DIAG
INT3
S
dog
D3
IN+
)
<
Conversion Data: MSBs
80Ω and the clock frequency is
S
S
INST2
Auto-
Address of Sequencer
x f
x f
INT2
Sequencer Address to
Zero
8/12
Test
= 0
D2
CLK
CLK
Instruction being
Generate INT1
Executed
Pause
INST1 INST0
Reset
Timer
INT1
RAM Pointer
>
>
D1
/
/
<
<
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Loop
Sync
Start
INT0
Sign
Sign
D0
S