lm12l458civf National Semiconductor Corporation, lm12l458civf Datasheet - Page 24

• Manufacturer Part Number: lm12l458civf
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

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2.0 Internal User-Programmable
Registers
is equal to the value stored in Bits 8–10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to “1”,
an external interrupt will appear at pin 31 (INT).
The value stored in bits 8–10 ranges from 000 to 111,
representing 0 to 7 instructions stored in the Instruction
RAM. After the Instruction RAM has been programmed and
the RESET bit is set to “1”, the Sequencer is started by
placing a “1” in the Configuration register’s START bit. Set-
ting the INT 1 trigger value to 000 does not generate an
INT 1 the first time the Sequencer retrieves and decodes
Instruction 000. The Sequencer generates INT 1 (by placing
a “1” in the Interrupt Status register’s Bit 1) the second time
and after the Sequencer encounters Instruction 000. It is
important to remember that the Sequencer continues to
operate even if an Instruction interrupt (INT 1) is internally or
externally generated. The only mechanisms that stop the
Sequencer are an instruction with the PAUSE bit set to “1”
(halts before instruction execution), placing a “0” in the Con-
figuration register’s START bit, or placing a “1” in the Con-
figuration register’s RESET bit.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable
register is set to “1”, an external interrupt will appear at pin
31 (INT).
3.0 Other Registers and Functions
3.1 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW = 0) or 1010x (A4–A0, BW = 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is
enabled or disabled in the Interrupt Enable register. Any of
the active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0 is set to “1” when a “watchdog” comparison limit
interrupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the
address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 4 is set to “1” when an auto-zero and full linearity self-
calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been gener-
ated.
Bit 6 is a “Don’t Care”.
Bit 7 is set to “1” when the LM12L458 return from power-
down to active mode.
Bits 8–10 hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
(Continued)
24
3.2 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1,
BW = 0) or 1101x (A4–A0, BW = 1). This register is used in
tandem with the Limit #1 and Limit #2 registers in the Instruc-
tion RAM. Whenever a given instruction’s input voltage ex-
ceeds the limit set in its corresponding Limit register (#1 or
#2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a
device reset is issued (see Bit 1 in the Configuration regis-
ter). This register holds the status of limits #1 and #2 for each
of the eight instructions.
Bits 0–7 show the Limit #1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #1 reg-
ister. When, for example, instruction 3 is a “watchdog” op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruc-
tion 3’s Limit #1 register, Bit 3 in the Limit Status register will
be set to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #2 reg-
ister. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
3.3 TIMER
The LM12L458 have an on-board 16-bit timer that includes a
5-bit pre-scaler. It uses the clock signal applied to pin 23 as
its input. It can generate time intervals of 0 through 2
cycles in steps of 2
the execution of instructions. It can also be used to slow the
conversion rate when converting slowly changing signals.
This can reduce the amount of redundant data stored in the
FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is pre-
loaded automatically. Bits 0–7 hold the preset value’s low
byte and Bits 8–15 hold the high byte. The Timer is activated
by the Sequencer only if the current instruction’s Bit 9 is set
(“1”). If the equivalent decimal value “N” (0 ≤ N ≤ 2
written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Se-
quencer will delay the same instruction’s execution by halt-
ing at state 3 (S3), as shown in Figure 15, for 32 x N + 2
clock cycles.
3.4 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The
voltage on the INT pin goes low at the same time as the
voltage on the DMARQ pin goes high. The voltage on the
DMARQ pin goes low when the FIFO is emptied. The Inter-
rupt Status register must be read to clear the FIFO interrupt
flag in order to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
data bus connection (a logic “0” applied to the BW pin).
Using this bus width allows DMA controllers that have single
address Read/Write capability to easily unload the FIFO.
Using DMA on an 8-bit data bus is more difficult. Two read
operations (low byte, high byte) are needed to retrieve each
5
. This time interval can be used to delay
16
21
− 1) is
clock