dac1008 National Semiconductor Corporation, dac1008 Datasheet - Page 18

• Manufacturer Part Number: dac1008
• Description: Up Compatible, Double-buffered D To A Converters
• Manufacturer: National Semiconductor Corporation

the requirements of the DAC (with regard to left justified
data) and the implementation of the PUSH instruction which
will output the higher order byte of the register pair (i e
register B of the BC pair) first The DAC will actually appear
as a two-byte ‘‘stack’’ in memory to the CPU The auto-dec-
rementing of the stack pointer during a PUSH allows using
address bit 0 of the stack pointer as the Byte1 Byte2 and
XFER strobes if bit 0 of the stack pointer address
(SP
dress decoding by the DM8131 will generate a unique DAC
chip select (CS) and synchronize this CS to the two memory
write strobes of the PUSH instruction
To reset the stack pointer so new data may be output to the
same DAC a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair be-
fore it is ‘‘PUSHED’’ to the DAC should be executed as the
POP instruction will arbitrarily alter the contents of a register
pair
Another double byte write instruction is Store H and L Direct
(SHLD) where the HL register pair would temporarily con-
tain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code The auto in-
crementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer strobes
7 2 DAC1006 to MC6820 1 PIA Interface
In Figure 19 the DAC1006 is interfaced to an M6800 system
through an MC6820 1 Peripheral Interface Adapter (PIA) In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary Furthermore by using both Ports A
and B of the PIA the 10-bit data transfer assumed left
justified again in two 8-bit bytes is greatly simplified The
HIGH byte is loaded into Output Register A (ORA) of the
b
1) is a ‘‘1’’ as presented to the DAC Additional ad-
FIGURE 19 DAC1000 to MC6820 1 PIA Interface
b
1
18
PIA and the LOW byte is loaded into ORB The 10-bit data
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control The 10-bit data word in the DAC register
will be latched (and hence V
brought back HIGH
If both output ports of the PIA are not available it is possible
to interface the DAC1006 through a single port without
much effort However additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required
7 3 Noise Considerations
A typical digital microprocessor bus environment is a tre-
mendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry The fast edges
of the data and address bus signals generate frequency
components of 10’s of megahertz and can cause noise
spikes to appear at the DAC output These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device
In low frequency or DC applications low pass filtering can
reduce these noise spikes This is accomplished by over-
compensating the DAC output amplifier by increasing the
value of the feedback capacitor (C
In applications requiring a fast transient response from the
DAC and op amp filtering may not be feasible Adding a
latch DM74LS374 as shown in Figure 20 isolates the de-
vice from the data bus thus eliminating noise spikes that
occur every time the data bus changes state Another meth-
od for eliminating noise spikes is to add a sample and hold
after the DAC op amp This also has the advantage of elimi-
nating noise spikes when changing digital codes
OUT
will be fixed) when CB2 is
C
in Figure 3 )
TL H 5688 – 25