dac1008 National Semiconductor Corporation, dac1008 Datasheet - Page 3

• Manufacturer Part Number: dac1008
• Description: Up Compatible, Double-buffered D To A Converters
• Manufacturer: National Semiconductor Corporation

Output Leakage
Digital Input
Digital Input
Current Settling
Write and XFER
Data Set Up Time
Data Hold Time
Control Set Up
Control Hold Time
Electrical Characteristics
Tested at V
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2 All voltages are measured with respect to GND unless otherwise specified
Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking
Note 4 For current switching applications both I
degraded by approximately V
Note 5 Guaranteed at V
Note 6 T
Note 7 The unit ‘‘FSR’’ stands for ‘‘Full Scale Range ’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a
particular V
guarantees that after performing a zero and full scale adjustment (See Sections 2 5 and 2 6) the plot of the 1024 analog voltage outputs will each be within
0 05%
Note 8 This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
of only 100 ns The entire write pulse must occur within the valid data interval for the specified t
Note 9 Guaranteed by design but not tested
Note 10 A 200 nA leakage current with R
Note 11 Human body model 100 pF discharged through a 1 5 kX resistor
Current
Voltages
Currents
Time
Pulse Width
Time
c
Parameter
V
MIN
REF
REF
e
I
I
of a straight line which passes through zero and full scale
CC
OUT1
OUT2
0 C and T
value and to indicate the true performance of the part The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘0 05% of FSR (MAX) ’’ This
e
4 75 V
REF
MAX
t
t
t
t
t
t
S
W
DS
DH
CS
CH
e
OS
e
g
DC
d
70 C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts
10 V
V
and 15 75 V
REF
T
All data inputs
All data inputs
T
Low level
High level (all parts)
T
Digital inputs
Digital inputs
V
V
T
V
T
V
T
V
T
V
T
MIN s
MIN s
MIN s
MIN s
MIN s
MIN s
MIN s
MIN s
IL
IL
IL
IL
IL
IL
DC
latched low
latched high
LCN and LCWM suffix
e
e
e
e
e
e
For example if V
and V
T
T
T
T
T
0V V
0V V
0V V
OV V
0V V
0V V
fb
Conditions
A
A
A
A
A
e
T
T
T
T
T
T
T
T
e
e
e
e
e
A s
A s
A s
A s
A s
A s
A s
A s
20K and V
REF
25 C
25 C
25 C
25 C
25 C
IH
IH
IH
IL
IH
IH
OUT1
T
T
T
T
T
T
T
T
e
DC
e
e
e
e
e
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
e
k
l
g
5V
5V
5V
5V
5V
0 8V
2 0V
5V
1 V
and I
T
REF
REF
A
DC
e
e
OUT2
e
25 C V
10V corresponds to a zero error of (200
10V then a 1 mV offset V
must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier The linearity error is
Note
See
REF
10
6
6
6
8
9
9
9
9
9
e
3
10 000 V
Min
150
320
150
320
200
250
150
320
2 0
10
10
V
CC
to 15V
OS
DC
e
Typ
b
on I
500
100
120
100
120
100
1 0
12V
60
80
60
0
0
unless otherwise noted (Continued)
40
W
DC g
OUT1
t
DC g
DS
or I
c
5%
t
0 8 0 8
DH
b
10
5%
Max
a
OUT2
200
200
b
150
and t
10
9 c
will introduce an additional 0 01% linearity error
20
S
W
c
to apply
) of 320 ns A typical part will operate with t
10
Min
320
500
320
500
320
500
320
500
2 0
10
10
3
)
c
V
100
CC
d
e
Typ
b
500
200
250
170
250
220
320
180
260
10 which is 0 04% of FS
1 0
5V
0
0
40
DC g
0 7 0 8
5%
b
Max
a
200
200
150
10
mA
mA
Units
V
V
nA
nA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DC
DC
DC
DC
W