epm2210gm100i Altera Corporation, epm2210gm100i Datasheet - Page 55

• Manufacturer Part Number: epm2210gm100i
• Description: Section I. Max Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 3–1. MAX II Parallel Flash Loader
Notes to
(1)
(2)
In System
Programmability
Altera Corporation
December 2007
This block is implemented in LEs.
This function is supported in the Quartus II software.
Memory Device
Figure
Flash
DQ[7..0]
A[20..0]
RY/BY
3–1:
WE
OE
CE
TMS
TDO
TCK
TDI
MAX II devices can be programmed in-system via the industry standard
4-pin IEEE Std. 1149.1 (JTAG) interface. In-system programmability (ISP)
offers quick, efficient iterations during design development and
debugging cycles. The logic, circuitry, and interconnects in the MAX II
architecture are configured with flash-based SRAM configuration
elements. These SRAM elements require configuration data to be loaded
each time the device is powered. The process of loading the SRAM data
is called configuration. The on-chip configuration flash memory (CFM)
block stores the SRAM element’s configuration data. The CFM block
stores the design’s configuration pattern in a reprogrammable flash array.
During ISP, the MAX II JTAG and ISP circuitry programs the design
pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high
programming voltages required to program the CFM cells, allowing
in-system programming with any of the recommended operating
external voltage supplies (that is, 3.3 V/2.5 V or 1.8 V for the MAX IIG
and MAX IIZ devices). ISP can be performed anytime after V
V
configuration power-up time. By default, during in-system
CCIO
RUNIDLE_U
banks have been fully powered and the device has completed the
UPDATE_U
CLKDR_U
USER1_U
SHIFT_U
Core Version a.b.c variable
TDO_U
TMS_U
TCK_U
TDI_U
MAX II Device
Flash Loader
Configuration
DQ[7..0]
A[20..0]
OE
WE
CE
RY/BY
Parallel
(1), (2)
Logic
JTAG and In-System Programmability
MAX II Device Handbook, Volume 1
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Altera FPGA
CCINT
and all
3–5