epm2210gm100i Altera Corporation, epm2210gm100i Datasheet - Page 80

• Manufacturer Part Number: epm2210gm100i
• Description: Section I. Max Ii Device Family Data Sheet
• Manufacturer: Altera Corporation

Power Consumption
Power
Consumption
Timing Model
and
Specifications
Figure 5–2. MAX II Device Timing Model
5–10Core Version a.b.c variable
MAX II Device Handbook, Volume 1
I/O Pin
INPUT
I/O Input Delay
t
IN
f
Input Routing
Global Input Delay
Memory
Delay
Flash
User
t
DL
t
GLOB
Designers can use the Altera
PowerPlay Power Analyzer to estimate the device power.
For more information about these power analysis tools, refer to the
Understanding and Evaluating Power in MAX II Devices
MAX II Device Handbook and the
volume 3 of the Quartus II Handbook.
MAX II devices timing can be analyzed with the Altera Quartus
software, a variety of popular industry-standard EDA simulators and
timing analyzers, or with the timing model shown in
MAX II devices have predictable internal delays that enable the designer
to determine the worst-case timing of any design. The software provides
timing simulation, point-to-point delay prediction, and detailed timing
analysis for device-wide performance evaluation.
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Refer to the
MAX II Devices
information.
Data-In/LUT Chain
To Adjacent LE
Register Control
LUT Delay
t
Delay
Logic Element
LUT
t
C
chapter in the MAX II Device Handbook for more
t
R4
t
COMB
t
t
t
t
PRE
CLR
CO
SU
t
H
Register Delays
®
PowerPlay Early Power Estimator and
t
C4
PowerPlay Power Analysis
Data-Out
Combinational Path Delay
From Adjacent LE
Output Routing
t
Delay
FASTIO
t
IODR
t
IOE
Understanding Timing in
Output and Output Enable
Figure
chapter in the
Data Delay
Altera Corporation
Output
Delay
t
t
t
OD
XZ
ZX
chapter in
5–2.
July 2008
®
II
I/O Pin