xcr3320 Xilinx Corp., xcr3320 Datasheet
xcr3320
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xcr3320 Summary of contents
Page 1
... Versatile XOR allows an 8-bit XOR function to be imple- mented in only 20 product terms, compared to 65 product terms for the traditional XOR approach. The XCR3320 is SRAM-based, which means that it is con- figured from an external source at power up. See the con- figuration section of this data sheet for more information. ...
Page 2
... Sparc, and HP platforms. Device fitting uses a Xilinx developed tool including WebFITTER. XPLA2 Architecture Figure 1 shows a high level block diagram of the XCR3320 implementing the XPLA2 architecture. The XPLA2 archi- tecture is a multi-level, modular hierarchy that consists of Fast Modules interconnected by a virtual crosspoint switch ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD XPLA2 Fast Module Each Fast Module consists of four Logic Blocks of 20 mac- rocells each. Depending on the package, either seven the 20 macrocells in each Logic Block are connected to I/O pins, and the remaining macrocells are used as bur- ied nodes ...
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... This product has been discontinued. Please see R LZIA INPUTS 36 CONTROL PAL ARRAY 4 PLA ARRAY (32) Figure 3: Xilinx XPLA2 Logic Block Architecture DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD 8 PATENT PENDING www.xilinx.com 1-800-255-7778 for details. MC0 MC1 MC2 MC19 SP00589A 4 ...
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... XCR3320: 320 Macrocell SRAM CPLD XPLA2 Macrocell Architecture Figure 4 shows the XPLA2 macrocell architecture used in the XCR3320. The macrocell can be configured as either T-type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters ...
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... This product has been discontinued. Please see R Simple Timing Model Figure 5 shows the XCR3320 timing model. The XCR3320 timing model is very simple compared to the models of competing architectures. There are three main timing parameters: the pin-to-pin delay for combinatorial logic functions (t ...
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... This also makes it possible to manufacture high density CPLDs like the XCR3320 that consume a fraction of the power of competing devices. Refer to Table 1 showing the I TotalCMOS CPLD (data taken with 20 16-bit counters at 3 ...
Page 8
... There are three basic configuration methods: master, slave, and peripheral. The configuration data can be transmitted to the XCR3320 serially or in parallel bytes master, the XCR3320 generates the clock and control signals to strobe configuration data into the XCR3320 slave device, a clock is generated externally, and provided into the XCR3320s cclk pin ...
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... XCR3320. The development system is used to generate configuration data in the JEDEC <design>.jed file, there are two general methods of con- figuring the XCR3320. The utility download can load the jed2mcs PROM PROGRAMMER Figure 7: Design Flow 9 www.xilinx.com/partinfo/notify/pdn0007.htm configuration data from workstation hard disk into the XCR3320 ...
Page 10
... When configuration is initiated, a counter in the XCR3320 is set to zero and begins to count configuration clock cycles applied to the XCR3320. As each configuration data frame is supplied to the XCR3320 internally assembled into data words. Each data word is loaded into the internal con- figuration memory. The configuration loading process is ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD pord prgmn t crcerrn resetn cclk t smode M[3:0] I/O active done t IL hdc ldcn INITIALIZATION Figure 9: General Configuration Mode Timing Diagram 11 www.xilinx.com/partinfo/notify/pdn0007.htm r t cclk t CL CONFIGURATION START UP www.xilinx.com 1-800-255-7778 for details. ...
Page 12
... Upon power-up, the device goes through an initialization process. First, an internal power-on-reset circuit is trig- gered when power is applied. When V age at which portions of the XCR3320 begin to operate (1.5V), the configuration pins are set to be inputs or outputs based on the configuration mode, as determined by the mode select inputs M[2:0]. The mode pins must be stable ...
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... START UP The flip-flops are reset one cycle after done goes high so that operation begins in a known state. The done outputs from multiple XCR3320s can be wire ANDed and used as an active-high ready signal, to disable PROMs with delay active-low enable(s reset to other parts of the system ...
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... There are four types of data frames. The header is shifted into the device first, followed by one data frame. Configura- tion of a single XCR3320 requires 338 data packets, one for each address. All preceding data must contain only 1’s. Once a device is configured, it retransmits data of any polarity. Before and during configuration, all data retrans- mitted out the daisy-chain port (dout) are 1’ ...
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... This field is only used by LSB a XCR3320 the master mode. SP00595 Device ID: This is a 32-bit field containing XCR3320 device ID: 0000_001_001_010000_1_000_00000010101_1 User Code: This is a 216 bit field reserved for user information. ISC Code Frame The isc_code address is 337. ...
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... EEPROMs. This restarts the config- uration process. package. Serial The XCR3320 done pin is routed to the CE pin of the EEPROMs. The Low signal on done during configuration enable the serial EEPROMs. At the completion of configu- ration, the High on done disables the EEPROMs. ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD DATA CLK CE RESET/OE CEO Figure 17: Master Serial Configuration CCLK t S DIN DOUT Figure 18: Master Serial Configuration Mode Timing Diagram Table 5: Master Serial Configuration Mode Timing Characteristics Symbol t din setup time ...
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... XCR3320 increments the address for each byte loaded. The starting address is output when the device enters the configuration state. The XCR3320 latches the data byte on the second rising edge of cclk. This next data byte is latched in the XCR3320 seven cclk cycles later. ...
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... MHz. Also note that CS1 is a multi-function pin, which means that it is available as a user I/O during normal device operation. As with all user I/O on the XCR3320, CS1 has an internal pull-down resistor that is automatically activated if the I/O pin is not used (see information) ...
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... Symbol t D[7:0] setup time S t D[7:0] hold time H t cclk high time CH t cclk low time CL f cclk frequency C DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD Parameter Single device Daisy-chain device Single device Daisy-chain device ...
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... In daisy-chained operation, all down- stream devices use slave serial mode regardless of the configuration mode of the lead device. Multiple slave XCR3320s can be loaded with identical con- figurations simultaneously. This is done by loading the con- figuration data into the din inputs in parallel. ...
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... High. Subsequent data bytes are clocked in on every eighth rising edge of cclk. The process repeats until all of the data is loaded into the XCR3320. The serial data begins shifting out on dout 0.5 MICRO– PROCESSOR Figure 25: Slave Parallel Configuration Schematic DS033 (v1 ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD CCLK hdc D[7:0] BYTE 0 DOUT Figure 26: Slave Parallel Configuration Mode Timing Diagram Table 9: Slave Parallel Configuration Mode Timing Characteristics Symbol t D[7:0] setup time S t D[7:0] hold time H t cclk high time CH t cclk low time ...
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... Daisy Chain Operation Multiple XCR3320s can be configured by using a daisy-chain of XCR3320s. Daisy-chaining uses a lead XCR3320 and one or more XCR3320s configured in slave serial mode. The lead XCR3320 can be configured in any mode. Figure 27 shows the connections for loading multi- ple XCR3320s in a daisy-chain configuration with the lead devices configured in master parallel mode. shows the connections for loading multiple XCR3320’ ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD V CC cclk cclk din dout V CC EEPROM pgrmn resetn reset/ Figure 28: Daisy Chain Schematic with Master Serial Lead Device 25 www.xilinx.com/partinfo/notify/pdn0007.htm cclk dout din MASTER SERIAL SLAVE #1 ...
Page 26
... Reduces spare board inventories The Xilinx XCR3320's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Xilinx XCR3320, the TAP Port includes five pins (refer to Table 10) described in the JTAG specification and t ...
Page 27
... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD Table 12: XCR3320 Low-Level JTAG Boundary-Scan Commands Instruction (Instruction Code) Register Used SAMPLE/PRELOAD The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal (00010) operation of the component to be taken and examined. It also allows data values to be ...
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... H t tck high time CH t tck low time CL f tck frequency TCK t tck to tdo delay D DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD Parameter www.xilinx.com 1-800-255-7778 for details. SP00613 Min Max. ...
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... XCR3320: 320 Macrocell SRAM CPLD Device Configuration Through JTAG In addition to the normal configuration modes, the XCR3320 can also be configured through the JTAG port. This feature is very useful for design prototyping and debug before the device is put into the final product. In System ...
Page 30
... I/O capacitance IO C Clock pin capacitance T CLK R done pull-up resistor DONE R Unused I/O pull-down PD resistor I Input leakage OZH I Input leakage OZL DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD 1 Min -0.5 -1.2 -0.5 -30 -40 -65 Voltage 3.3V ±10% 3.3V ±10% < AMB Test Conditions ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD AC Electrical Characteristics For Commercial Grade Devices Commercial temperature range 3.0V to 3.6V < Symbol Timing Requirements t Clock LOW time CL t Clock HIGH time CH t PAL setup time (Global clock) SU_PAL ...
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... Clock pin capacitance T CLK R done pull-up resistor DONE R Unused I/O pull-down PD resistor I Input leakage OZH I Input leakage OZL DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD < AMB Test Conditions 5. output loads, inputs at V amb ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD AC Electrical Characteristics For Industrial Grade Devices Industrial temperature range 3.0V to 3.6V; -40 C < Symbol Timing Requirements t Clock LOW time CL t Clock HIGH time CH t PAL setup time (Global clock) SU_PAL ...
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... DUT OUTPUT Voltage Waveform +3. 2.0 ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD SP00629 90% 10% 2.0 ns SP00630 www.xilinx.com 1-800-255-7778 for details. 34 ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD Device Pin Diagrams XCR3320 256-pin Plastic BGA www.xilinx.com/partinfo/notify/pdn0007.htm BOTT OM VIEW www ...
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... F1_0_5* B17 GND D17 F1_0_9 B18 F1_2_8 D18 GND B19 F1_2_7 D19 F1_2_11 B20 F1_2_6* D20 *Represents multi-function pin DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD Function Pkg Ball Function Pkg Ball F0_0_2* E1 clk_3 L1 F0_0_3 E2 gts L2 F0_0_4* E3 GND L3 F0_0_5 E4 ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD 260-pin Description Table Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5. Table 16: Pin Description Symbol Pin Numbers Type V D7, D8, D10 D11, D13, D14, D15, G4, ...
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... See “Terminations” on page 8 crcerrn goes Low when the XCR3320 detects a CRC error or an invalid peramble during configuration. The XCR3320 that detected the error will go into the initialization state and will not resume configuration until prgmn and resetn are both high. Once configuration has resumed crcerrn will go high ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD XCR3320 - 160-Pin Plastic TQFP www.xilinx.com/partinfo/notify/pdn0007.htm 160 121 TQFP 41 80 www.xilinx.com 1-800-255-7778 for details. R 120 81 SP00672 DS033 (v1.3) October 9, 2000 ...
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... F3_2_1 F3_2_2 75 36 F3_2_3 F3_2_4 77 38 F3_2_5 78 39 F3_2_6 *Represents multi-function pins DS033 (v1.3) October 9, 2000 www.xilinx.com/partinfo/notify/pdn0007.htm XCR3320: 320 Macrocell SRAM CPLD Function Number Function TCK V CC TDI 82 F2_0_6* TMS 83 F2_0_5 TDO 84 F2_0_4 F3_0_6 85 F2_0_3* F3_0_5* 86 F2_0_2 GND 87 ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD 160 Pin Description Table Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5. Table 18: Pin Function Description Symbol Pin Number Type V 15, 23, 40, 53 62, 71, 80, 81, ...
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... See “Terminations” on page 8 crcerrn goes Low when the XCR3320 detects a CRC error or an invalid peramble during configuration. The XCR3320 that detected the error will go into the initialization state and will not resume configuration until prgmn and resetn are both High. Once configuration has resumed crcerrn will go High ...
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... This product has been discontinued. Please see XCR3320: 320 Macrocell SRAM CPLD Ordering Information Example: XCR3320 -7 TQ 160 C Device Type Speed Options Speed Options -10 pin-to-pin delay - pin-to-pin delay -7: 7.5 ns pin-to-pin delay Component Availability Pins 160 Type ...