xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 13

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xcr3320

Manufacturer Part Number
xcr3320
Description
Xcr3320 320 Macrocell Sram Cpld
Manufacturer
Xilinx Corp.
Datasheet

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This product has been discontinued. Please see
XCR3320: 320 Macrocell SRAM CPLD
Figure 10: Using GTS Signal with Power Up to Avoid Signal Contention with Multi-function Pins Used as I/O
are used as I/O after configuration is finished. Holding gts
high until after the multi-function pins are disconnected
from the driving source allows these pins to transition from
configuration pins to user definable I/O without signal con-
tention. In this case, the I/O become active a t
after the gts pin is pulled low.
13
I/O active
crcerrn
prgmn
resetn
M[3:0]
done
GTS
V
ldcn
cclk
hdc
DD
INITIALIZATION
t
t
pord
smode
t
IL
t
r
www.xilinx.com/partinfo/notify/pdn0007.htm
CONFIGURATION
GTSR
t
CL
www.xilinx.com
1-800-255-7778
delay
t
The flip-flops are reset one cycle after done goes high so
that operation begins in a known state. The done outputs
from multiple XCR3320s can be wire ANDed and used as
an active-high ready signal, to disable PROMs with
active-low enable(s), or to reset to other parts of the system
(see
HMODE
START UP
Figure
t
gtsr
27).
OPERATIONAL
for details.
t
gtsh
DS033 (v1.3) October 9, 2000
t
smode
INITIALIZATION
SP00653
t
PW
R

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