saf7118 NXP Semiconductors, saf7118 Datasheet - Page 116

no-image

saf7118

Manufacturer Part Number
saf7118
Description
Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
saf7118E
Manufacturer:
NXP
Quantity:
5 510
Part Number:
saf7118E
Manufacturer:
OMRON
Quantity:
5 510
Part Number:
saf7118EH
Manufacturer:
PHILIPS
Quantity:
252
Part Number:
saf7118EH/V1
Manufacturer:
INFINEON
Quantity:
101
Part Number:
saf7118EH/V1/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
saf7118EH/V1/G,557
Manufacturer:
FREESCALE
Quantity:
101
Part Number:
saf7118EH/V1/G,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
saf7118H/V1,557
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
Philips Semiconductors
Table 58:
SAF7118_3
Product data sheet
Bit
D7
D6
D[5:4]
D3
D[2:0]
RT/X port output control; 13h[7:0]
10.2.20 Subaddress 13h
Description
RTCO output enable
X port XRH output selection
X port XRV output selection
horizontal lock indicator
selection
XPD7 to XPD0 (port output
format selection); see
Section 9.5
Symbol
RTCE
XRHS
XRVS[1:0]
HLSEL
OFTS[2:0]
Rev. 03 — 16 February 2006
Multistandard video decoder with adaptive comb filter
Value
0
1
0
1
00
01
10
11
0
1
000
001
010
011
100
101
110
111
Function
3-state
enabled
HREF; see
HS:
V123 (see
ITU 656 related field ID (see
Figure 30
inverted V123
inverted ITU 656 related field ID
copy of inverted HLCK status bit (default)
fast horizontal lock indicator (for special
applications only)
ITU 656
ITU 656 like format with modified field blanking
according to VGATE position (programmable via
VSTA[8:0] 17h[0] 15h[7:0], VSTO[8:0] 17h[1]
16h[7:0] and VGPS[17h[2]])
Y-C
inserted)
reserved
multiplexed AD2/AD1 or AD4/AD3 bypass
(bits D8 to D1) dependent on mode settings
(see
AD2/AD4 is output at CREF = 1 and AD1/AD3 is
output at CREF = 0
multiplexed AD2/AD1 or AD4/AD3 bypass
(bits D7 to D0) dependent on mode settings
(see
AD2/AD4 is output at CREF = 1 and AD1/AD3 is
output at CREF = 0
reserved
multiplexed ADC MSB/LSB bypass dependent on
mode settings; only one ADC should be selected
at a time; ADx8 to ADx1 are outputs at CREF = 1
and ADx7 to ADx0 are outputs at CREF = 0
Programmable width in LLC8 steps via HSB[7:0]
06h[7:0] and HSS[7:0] 07h[7:0]
Fine position adjustment in LLC2 steps via
HDEL[1:0] 11h[5:4] (see
B
-C
Section
Section
R
4 : 2 : 2 8-bit format (no SAV/EAV codes
and
Figure 30
Figure 32
10.2.3); if two ADCs are selected
10.2.3); if two ADCs are selected
Figure
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
and
31)
Figure
Figure
SAF7118
31)
32)
116 of 170

Related parts for saf7118