saf7118 NXP Semiconductors, saf7118 Datasheet - Page 154

no-image

saf7118

Manufacturer Part Number
saf7118
Description
Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
saf7118E
Manufacturer:
NXP
Quantity:
5 510
Part Number:
saf7118E
Manufacturer:
OMRON
Quantity:
5 510
Part Number:
saf7118EH
Manufacturer:
PHILIPS
Quantity:
252
Part Number:
saf7118EH/V1
Manufacturer:
INFINEON
Quantity:
101
Part Number:
saf7118EH/V1/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
saf7118EH/V1/G,557
Manufacturer:
FREESCALE
Quantity:
101
Part Number:
saf7118EH/V1/G,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
saf7118H/V1,557
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
Philips Semiconductors
Table 147: Characteristics
V
levels refer to drawings and conditions illustrated in
[1]
[2]
[3]
[4]
[5]
[6]
SAF7118_3
Product data sheet
Symbol
t
t
Data and control signal output timing X port, related to XCLK output (for XPCK[1:0]83h[5:4] = 00 is default)
C
t
t
Control signal output timing RT port, related to LLC output
C
t
t
ICLK output timing
C
T
t
t
Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 00 is default)
C
t
t
ICLK input timing
T
r
f
OHD;DAT
PD
OHD;DAT
PD
r
f
OHD;DAT
o(d)
DDD
cy
cy
L
L
L
L
8-bit image port output mode, expansion port is 3-stated.
ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4.
V
V
The levels must be measured with load circuits; 1.2 k at 3 V (TTL load); C
The effects of rise and fall times are included in the calculation of t
illustrated in
The crystal oscillator drive level is typical 0.28 mW.
= 3.0 V to 3.6 V; V
DD(I2C)
IL(SCL,SDA)(max)
is the supply voltage of the I
Figure
Parameter
duty factors for
t
rise time
fall time
output load
capacitance
output data hold
time
propagation delay
from positive edge
of XCLK output
output load
capacitance
output hold time
propagation delay
from positive edge
of LLC output
output load
capacitance
cycle time
duty factors for
t
rise time
fall time
output load
capacitance at all
outputs
output data hold
time
output delay time
cycle time
XCLKH
ICLKH
= 1.5 V. For V
89.
/t
DDA
/t
ICLKL
XCLKL
= 3.1 V to 3.5 V; T
…continued
DD(I2C)
2
= 3.3 V then V
C-bus. For V
Conditions
0.6 V to 2.6 V
2.6 V to 0.6 V
C
C
C
C
0.6 V to 2.6 V
2.6 V to 0.6 V
C
C
L
L
L
L
L
L
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 15 pF
amb
DD(I2C)
Rev. 03 — 16 February 2006
IH(SCL,SDA)(min)
= 40 C to +85 C (typical values measured at T
Figure
= 3.3 V then V
89; unless otherwise specified.
Multistandard video decoder with adaptive comb filter
= 2.3 V; for V
OHD;DAT
IL(SCL,SDA)(max)
and t
L
= 50 pF.
DD(I2C)
PD
. Timings and levels refer to drawings and conditions
Min
35
-
-
15
4
-
15
4
-
15
31
35
-
-
15
4
-
31
= 5 V then V
= 1 V; for V
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
DD(I2C)
IH(SCL,SDA)(min)
= 5 V then
amb
Max
65
5
5
50
-
19
50
-
19
50
45
65
5
5
50
-
19
100
= 25 C); timings and
SAF7118
= 3.5 V.
154 of 170
[5]
Unit
%
ns
ns
pF
ns
ns
pF
ns
ns
pF
ns
%
ns
ns
pF
ns
ns
ns

Related parts for saf7118