saf7118 NXP Semiconductors, saf7118 Datasheet - Page 129

• Manufacturer Part Number: saf7118
• Description: Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 96:
Table 97:
Table 98:
[1]
SAF7118_3
Product data sheet
I port signal definitions
IGP0 is set to logic 0 (default polarity)
IGP0 is the output FIFO almost filled flag
IGP0 is the output FIFO overflow flag
IGP0 is the output FIFO almost full flag, level to be programmed in
subaddress 86h
IGP0 is the output FIFO almost empty flag, level to be programmed in
subaddress 86h
I port signal definitions
IGP1 is output field ID, as defined by OFIDC[90h[6]]
IGP1 is A/B task flag, as defined by CONLH[90h[7]]
IGP1 is sliced data flag, framing the sliced VBI data at the I port
IGP1 is set to logic 0 (default polarity)
IGP1 is the output FIFO almost filled flag
IGP1 is the output FIFO overflow flag
IGP1 is the output FIFO almost full flag, level to be programmed in
subaddress 86h
IGP1 is the output FIFO almost empty flag, level to be programmed in
subaddress 86h
I port output signal definitions
IGPH is a H gate signal, framing the scaler output
IGPH is an extended H gate (framing H gate during scaler output and
scaler input H reference outside the scaler window)
IGPH is a horizontal trigger pulse, on active going edge of H gate
IGPH is a horizontal trigger pulse, on active going edge of extended
H gate
IGPV is a V gate signal, framing scaled output lines
IGPV is the V reference signal from scaler input
IGPV is a vertical trigger pulse, derived from V gate
IGPV is a vertical trigger pulse derived from input V reference
X = don’t care.
I port signal definitions; global set 84h[7:6] and 86h[5]
I port signal definitions; global set 84h[5:4] and 86h[4]
I port output signal definitions; global set 84h[3:0]
Rev. 03 — 16 February 2006
Multistandard video decoder with adaptive comb filter
[1]
…continued
Control bits
86h[5]
IDG02
0
1
1
1
1
Control bits
86h[4]
IDG12
0
0
0
0
1
1
1
1
Control bits D3 to D0
IDV1
X
X
X
X
0
0
1
1
IDV0
X
X
X
X
0
1
0
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
84h[7:6]
IDG01
1
0
0
1
1
84h[5:4]
IDG11
0
0
1
1
0
0
1
1
IDH1
0
0
1
1
X
X
X
X
SAF7118
IDG00
1
0
1
0
1
IDG10
0
1
0
1
0
1
0
1
IDH0
0
1
0
1
X
X
X
X
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