saf7118 NXP Semiconductors, saf7118 Datasheet - Page 128

• Manufacturer Part Number: saf7118
• Description: Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 93:
[1]
[2]
Table 94:
Table 95:
[1]
Table 96:
SAF7118_3
Product data sheet
I port and scaler back-end clock selection
ICLK output and back-end clock is line-locked clock LLC from decoder
ICLK output and back-end clock is XCLK from X port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data outside the
scaling region
Output clock phase control
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by approximately 3 ns
XCLK output inverted and shifted by approximately 3 ns
X port I/O enable
X port output is disabled by software
X port output is enabled by software
X port output is enabled by pin XTRI at logic 0
X port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means
the SAF7118 is ready to receive data)
I port signal definitions
IGP0 is output field ID, as defined by OFIDC[90h[6]]
IGP0 is A/B task flag, as defined by CONLH[90h[7]]
IGP0 is sliced data flag, framing the sliced VBI data at the I port
X = don’t care.
Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
X = don’t care.
Global control 1; global set 80h[3:0]
X port I/O enable and output clock phase control; global set 83h[5:4]
X port I/O enable and output clock phase control; global set 83h[2:0]
I port signal definitions; global set 84h[7:6] and 86h[5]
10.7.2 Subaddresses 83h to 87h
Rev. 03 — 16 February 2006
[1]
Multistandard video decoder with adaptive comb filter
Control bits D3 to D0
ICKS3
X
X
X
X
X
X
0
1
Control bits D5 and D4
XPCK1
0
0
1
1
Control bits D2 to D0
XRQT
X
X
X
X
0
1
Control bits
86h[5]
IDG02
0
0
0
[1]
ICKS2
X
X
X
X
0
1
X
X
[2]
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
XPE1
0
0
1
1
X
X
84h[7:6]
IDG01
0
0
1
ICKS1
0
0
1
1
X
X
X
X
XPCK0
0
1
0
1
SAF7118
XPE0
0
1
0
1
X
X
IDG00
0
1
0
ICKS0
0
1
0
1
X
X
X
X
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