saa7105h-v1 NXP Semiconductors, saa7105h-v1 Datasheet - Page 12

• Manufacturer Part Number: saa7105h-v1
• Description: Digital Video Encoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.7
The functions scaling, Anti-Flicker Filter (AFF) and
re-interlacing are implemented in the vertical scaler.
Besides the entire input frame, it receives the first and last
lines of the border to allow anti-flicker filtering.
The circuit generates the interlaced output fields by scaling
down the input frames with different offsets for odd and
even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off;
see Table 85.
An additional, programmable vertical filter supports the
anti-flicker function. This filter is not available at upscaling
factors of more than 2.
The programming is similar to the horizontal scaler. For the
re-interlacing, the resolutions of the offset registers are not
sufficient, so the weighting factors for the first lines can
also be adjusted. YINC = 0 sets the scaling factor to 1;
YIWGTO and YIWGTE must not be 0.
Due to the re-interlacing, the circuit can perform upscaling
by a maximum factor of 2. The maximum factor depends
on the setting of the anti-flicker function and can be derived
from the formulae given in Section 7.20.
An additional upscaling mode allows to increase the
upscaling factor to maximum 4 as it is required for the old
VGA modes like 320
7.8
The FIFO acts as a buffer to translate from the PIXCLK
clock domain to the XTAL clock domain. The write clock is
PIXCLK and the read clock is XTAL. An underflow or
overflow condition can be detected via the I
access.
In order to avoid underflows and overflows, it is essential
that the frequency of the synthesized PIXCLK matches to
the input graphics resolution and the desired scaling
factor.
7.9
When the graphics picture is to be displayed as interlaced
PAL, NTSC, S-video or RGB on a TV screen, it is desired
in many cases not to lose picture information due to the
inherent overscanning of a TV set. The desired amount of
underscan area, which is achieved through appropriate
scaling in the vertical and horizontal direction, can be filled
in the border generator with an arbitrary true colour tint.
2004 Mar 04
Digital video encoder
Vertical scaler and anti-flicker filter
FIFO
Border generator
240.
2
C-bus read
12
7.10
The master clock generation is realized as a 27 MHz
crystal oscillator, which can operate with either a
fundamental wave crystal or a 3rd-harmonic crystal.
The crystal clock supplies the DTO of the pixel clock
synthesizer, the video encoder and the I
block. It also usually supplies the triple DAC, with the
exception of the auxiliary VGA or HDTV mode, where the
triple DAC is clocked by the pixel clock (PIXCLK).
The DTO can be programmed to synthesize all relevant
pixel clock frequencies between circa 40 and 85 MHz.
Two programmable dividers provide the actual clock to be
used externally and internally. The dividers can be
programmed to factors of 1, 2, 4 and 8. For the internal
pixel clock, a divider ratio of 8 makes no sense and is thus
forbidden.
The internal clock can be switched completely to the pixel
clock input. In this event, the input FIFO is useless and will
be bypassed.
The entire pixel clock generation can be locked to the
vertical frequency. Both pixel clock dividers get
re-initialized every field. Optionally, the DTO can be
cleared with each V-sync. At proper programming, this will
make the pixel clock frequency a precise multiple of the
vertical and horizontal frequencies. This is required for
some graphic controllers.
7.11
This block reduces the phase jitter of the synthesized pixel
clock. It works as a tracking filter for all relevant
synthesized pixel clock frequencies.
7.12
7.12.1
The encoder generates luminance and colour subcarrier
output signals from the Y, C
which are suitable for use as CVBS or separate Y and C
signals.
Input to the encoder, at 27 MHz clock (e.g. DVD), is either
originated from computer graphics at pixel clock, fed
through the FIFO and border generator, or a ITU-R BT.656
style signal.
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
V
IDEO PATH
SAA7104H; SAA7105H
B
and C
R
Product specification
baseband signals,
2
C-bus control