saa7105h-v1 NXP Semiconductors, saa7105h-v1 Datasheet - Page 65
saa7105h-v1
Manufacturer Part Number
saa7105h-v1
Description
Digital Video Encoder
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7105H-V1.pdf
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Philips Semiconductors
12.1
Figure 17 shows a possible reconstruction filter for the
digital-to-analog converters. Due to its cut-off frequency of
12.2
The analog output voltages are dependent on the total
load (typical value 37.5 ), the digital gain parameters and
the I
settings).
The digital output signals in front of the DACs under
nominal (nominal here stands for the settings given in
Table 116 Digital output signals conversion range
12.3
Use separate ground planes for analog and digital ground.
Connect these planes only at one point directly under the
device, by using a 0
Use separate supply lines for analog and digital supply.
Place the supply decoupling capacitors close to the supply
pins.
Use L
the decoupling capacitors to minimize radiation energy
(EMC).
2004 Mar 04
Digital settings
Digital output
Analog settings
Analog output
6 MHz, it is not suitable for HDTV applications.
Digital video encoder
SET/OUT
2
C-bus settings of the DAC reference currents (analog
bead
Reconstruction filter
Analog output voltages
Suggestions for a board layout
(ferrite coil) in each digital supply line close to
CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE
resistor directly at the supply stage.
see Tables 40 to 47
e.g. B DAC = 1FH
1.23 V (p-p)
1014
see Tables 40 to 47
e.g. G DAC = 1BH
65
1.00 V (p-p)
Tables 40 to 47 for example a standard PAL or NTSC
signal) conditions occupy different conversion ranges, as
indicated in Table 116 for a
By setting the reference currents of the DACs as shown in
Table 116, standard compliant amplitudes can be
achieved for all signal combinations; it is assumed that in
subaddress 16H, parameter DACF = 0000b, that means
the fine adjustment for all DACs in common is set to 0%.
If S-video output is desired, the adjustment for the C
(chrominance subcarrier) output should be identical to the
one for VBS (luminance plus sync) output.
Place the analog coupling (clamp) capacitors close to the
analog input pins. Place the analog termination resistors
close to the coupling capacitors.
Be careful of hidden layout capacitors around the crystal
application.
Use serial resistors in clock, sync and data lines, to avoid
clock or data reflection effects and to soften data energy.
881
e.g. R DAC = G DAC = B DAC = 0BH
SAA7104H; SAA7105H
RGB, BLACK-TO-WHITE
100
100
see Table 35
0.70 V (p-p)
colour bar signal.
876
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