saa7105h-v1 NXP Semiconductors, saa7105h-v1 Datasheet - Page 19

• Manufacturer Part Number: saa7105h-v1
• Description: Digital Video Encoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The following Sections give the set of equations required
to program the IC for the most common application: A post
processor in master mode with non-interlaced video input
data.
Some variables are defined below:
7.20.1
At 60 Hz, the first visible pixel has the index 256,
710 pixels can be encoded; at 50 Hz, the index is 284,
702 pixels can be visible.
The output lines should be centred on the screen. It should
be noted that the encoder has 2 clocks per pixel;
see Table 58.
ADWHS = 256 + 710
ADWHS = 284 + 702
ADWHE = ADWHS + OutPix
For vertical, the procedure is the same. At 60 Hz, the first
line with video information is number 19, 240 lines can be
active. For 50 Hz, the numbers are 23 and 287;
see Table 64.
LAL = FAL + OutLin (all frequencies)
Most TV sets use overscan, and not all pixels respectively
lines are visible. There is no standard for the factor, it is
highly recommended to make the number of output pixels
and lines adjustable. A reasonable underscan factor is
10%, giving approximately 640 output pixels per line.
7.20.2
The total number of pixel clocks per line and the input
horizontal offset need to be chosen next. The only
constraint is that the horizontal blanking has at least
10 clock pulses.
2004 Mar 04
FAL
FAL
InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input field/frame
TPclk: the pixel clock period
RiePclk: the ratio of internal to external pixel clock
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output field
TXclk: the encoder clock period (37.037 ns).
Digital video encoder
=
=
19
23
TV
I
NPUT FRAME AND PIXEL CLOCK
+
+
DISPLAY WINDOW
240 OutLin
-------------------------------- -
287 OutLin
-------------------------------- -
–
–
2
2
OutPix (60 Hz);
OutPix (50 Hz);
(60 Hz);
(50 Hz);
2 (all frequencies)
19
The required pixel clock frequency can be determined in
the following way: Due to the limited internal FIFO size, the
input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to
process the first and last border lines for the anti-flicker
function. Thus:
and for the pixel clock generator
see Tables 67, 69 and 70. The divider PCLE should be set
according to Table 69. PCLI may be set to a lower or the
same value. Setting a lower value means that the internal
pixel clock is higher and the data get sampled up. The
difference may be 1 at 640
resolutions with 320 pixels per line as a rule of thumb. This
allows horizontal upscaling by a maximum factor of 2
respectively 4 (this is the parameter RiePclk).
The equations ensure that the last line of the field has the
full number of clock cycles. Many graphic controllers
require this. Note that the bit PCLSY needs to be set to
ensure that there is not even a fraction of a clock left at the
end of the field.
7.20.3
XOFS can be chosen arbitrarily, the condition being that
XOFS + XPIX
VESA display timings are preferred.
HLEN = InPpl
XINC needs to be rounded up, it needs to be set to 0 for a
scaling factor of 1.
TPclk
TPclk
PCL
PCLI
XPIX
XINC
=
=
=
=
=
=
TXclk
-------------- -
TPclk
PCLE
H
InPix
------------ -
OutPix
----------------- -
--------------------------------------------------------------------------------------- -
InPpl integer
--------------------------------------------------------------------------------------- -
InPpl integer
InPix
ORIZONTAL SCALER
2
–
262.5 1716 TXclk
312.5 1728 TXclk
2
RiePclk
HLEN is fulfilled. Values given by the
RiePclk
log
----------------------------
20
------------------- -
RiePclk
SAA7104H; SAA7105H
4096
+
log
RiePclk
PCLE
2
InLin
--------------------- -
InLin
--------------------- -
OutLin
OutLin
1
(all frequencies);
480 pixels resolution and 2 at
(all frequencies)
+
+
2
2
262.5
312.5
Product specification
(60 Hz)
(50 Hz)