saa7105h-v1 NXP Semiconductors, saa7105h-v1 Datasheet - Page 33

• Manufacturer Part Number: saa7105h-v1
• Description: Digital Video Encoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 36 Subaddress 3AH
Table 37 Subaddress 54H
Table 38 Subaddresses 55H to 59H
2004 Mar 04
CBENB
SYNTV
SYMP
DEMOFF
CSYNC
Y2C
UV2C
VPSEN
GPVAL
GPEN
EDGE
SLOT
VPS5
VPS11
VPS12
VPS13
VPS14
DATA BYTE
DATA BYTE
DATA BYTE
Digital video encoder
fifth byte of video programming system data
eleventh byte of video programming system data
twelfth byte of video programming system data
thirteenth byte of video programming system data
fourteenth byte of video programming system data
LOGIC
LEVEL
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
data from input ports is encoded
colour bar with fixed colours is encoded
in slave mode, the encoder is only synchronized at the beginning of an odd field; default
after reset
in slave mode, the encoder receives a vertical sync signal
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port
Y-C
Y-C
pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output
(at PIXCLK)
pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL
clock)
input luminance data is twos complement from PD input port
input luminance data is straight binary from PD input port; default after reset
input colour difference data is twos complement from PD input port
input colour difference data is straight binary from PD input port; default after reset
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
pin VSM provides a LOW level if GPEN = 1
pin VSM provides a HIGH level if GPEN = 1
pin VSM provides a vertical sync for a monitor; default after reset
pin VSM provides a constant signal according to GPVAL
input data is sampled with inverse clock edges
input data is sampled with the clock edges specified in Tables 8 to 13; default after reset
normal assignment of the input data to the clock edge; default after reset
correct time misalignment due to inverted assignment of input data to the clock edge
B
B
-C
-C
R
R
DESCRIPTION
to RGB dematrix is active; default after reset
to RGB dematrix is bypassed
33
DESCRIPTION
DESCRIPTION
in line 16; LSB first; all other bytes are not
relevant for VPS
SAA7104H; SAA7105H
REMARKS
Product specification