admc331 Analog Devices, Inc., admc331 Datasheet - Page 10

• Manufacturer Part Number: admc331
• Description: Single Chip Dsp Motor Controller
• Manufacturer: Analog Devices, Inc.

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ADMC331
PIN FUNCTION DESCRIPTION
The ADMC331 is available in an 80-lead TQFP package. Table I
contains the pin descriptions.
Pin
Group
Name
RESET
SPORT0
SPORT1
CLKOUT
CLKIN, XTAL
PIO0–PIO23
AUX0–AUX1
AH–CL
PWMTRIP
PWMPOL
PWMSYNC
PWMSR
V1–V3,
VAUX0–VAUX3 4
CAPIN
ICONST
VREF
AV
AGND
SGND
V
GND
INTERRUPT OVERVIEW
The ADMC331 can respond to 34 different interrupt sources
with minimal overhead, 8 of which are internal DSP core
interrupts and 26 interrupts from the motor control peripherals.
The 8 DSP core interrupts are SPORT0 receive and transmit,
SPORT1 receive (or IRQ0) and transmit (or IRQ1), the internal
timer and two software interrupts. The motor control peripheral
interrupts are the 24 peripheral I/Os and two from the PWM
(PWMSYNC pulse and PWMTRIP). All motor control inter-
rupts are multiplexed into the DSP core through the peripheral
IRQ2 interrupt. The interrupts are internally prioritized and indi-
vidually maskable. A detailed description of the entire inter-
rupt system of the ADMC331 is given later, following a more
detailed description of each peripheral block.
DD
DD
#
of
Pins Output Function
1
5
6
1
2
24
2
6
1
1
1
1
3
1
1
1
1
1
1
5
11
Table I. Pin List
Input/
I/P
I/P, O/P Serial Port 0 Pins (TFS0, RFS0,
I/P, O/P Serial Port 1 Pins (TFS1, RFS1,
O/P
I/P, O/P External Clock or Quartz Crystal
I/P, O/P Digital I/O Port Pins.
O/P
O/P
I/P
I/P
O/P
I/P
I/P
I/P
I/P
O/P
O/P
Processor Reset Input.
DT0, DR0, SCLK0).
DT1, DR1A, DR1B, SCLK1).
Processor Clock Output.
Connection Point.
Auxiliary PWM Outputs.
PWM Outputs.
PWM Trip Signal.
PWM Polarity Pin.
PWM Synchronization Pin.
Switch Reluctance Mode Pin.
Analog Inputs.
Auxiliary Analog Input
ADC Capacitor Input.
ADC Constant Current Source.
Voltage Reference Output.
Analog Power Supply.
Analog Ground.
Analog Signal Ground
Digital Power Supply.
Digital Ground.
Memory Map
The ADMC331 has two distinct memory types: program
memory and data memory. In general, program memory contains
user code and coefficients, while the data memory is used to store
variables and data during program execution. Both program
memory RAM and ROM are provided on the ADMC331. Pro-
gram memory RAM is arranged as one contiguous 2K × 24-bit
block, starting at address 0x0000. Program memory ROM is
located at address 0x0800. Data memory is arranged as a 1K ×
16-bit block starting at address 0x3800. The motor control
peripherals are memory mapped into a region of the data
memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
Address Range
0x0000–0x002F
0x0030–0x071F
0x0720–0x07EC
0x07ED–0x07FF
0x0800–0x0DEC
0x0DED–0x0FEA
0x0FEB–0x0FFF
Address Range
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x3B5F
0x3B60–0x3BFF
0x3C00–0x3FFF
ROM Code
The 2K × 24-bit block of program memory ROM starting at ad-
dress 0x0800 contains a monitor function that is used to download
and execute user programs via the serial port. In addition, the
monitor function supports an interactive mode in which commands
are received and processed from a host. An example of such a host
is the Windows
the software development system for the ADMC331. In the inter-
active mode, the host can access both the internal DSP and periph-
eral motor control registers of the ADMC331, read and write to
both program and data memory, implement breakpoints and per-
form single-step and run/halt operation as part of the program
debugging cycle.
In addition to the monitor function, the program memory ROM
contains a number of useful mathematical and motor control util-
ities that can be called as subroutines from the user code. A com-
plete list of these ROM functions is given in Table IV. The start
address of the function in the program memory ROM is also given.
Refer to the ADMC331 DSP Motor Controller Developer’s Reference
Manual for more details of the ROM functions.
®
Table II. Program Memory Map
-based Motion Control Debugger, which is part of
Table III. Data Memory Map
RAM
RAM
RAM
RAM
ROM
RAM
RAM
Memory
Type
ROM
ROM
Memory
Type
Function
Interrupt Vector Table
User Program Space
Reserved by Debugger
Reserved by Monitor
ROM Monitor
ROM Math and Motor
Control Utilities
Reserved
Function
Reserved
Memory Mapped Registers
Reserved
User Data Space
Reserved by Monitor
Memory Mapped Registers