admc331 Analog Devices, Inc., admc331 Datasheet - Page 15

• Manufacturer Part Number: admc331
• Description: Single Chip Dsp Motor Controller
• Manufacturer: Analog Devices, Inc.

Width of the PWMSYNC Pulse, PWMSYNCWT Register
The PWM controller of the ADMC331 produces an output
PWM synchronization pulse at a rate equal to the PWM switch-
ing frequency in single update mode and at twice the PWM
frequency in the double update mode. This pulse is available
for external use at the PWMSYNC pin. The width of this
PWMSYNC pulse is programmable by the 8-bit read/write
PWMSYNCWT register. The width of the PWMSYNC pulse,
T
so that the width of the pulse is programmable from t
(corresponding to 38.5 ns to 9.84 µs for a CLKOUT rate of
26 MHz). Following a reset, the PWMSYNCWT register con-
tains 0x27 (= 39) so that the default PWMSYNC width is
1.54 µs, again for a 26 MHz CLKOUT.
PWM Duty Cycles, PWMCHA, PWMCHB, PWMCHC
Registers
The duty cycles of the six PWM output signals on pins AH to
CL are controlled by the three 16-bit read/write duty-cycle
registers, PWMCHA, PWMCHB, and PWMCHC. The integer
value in the register PWMCHA controls the duty cycle of the
signals on AH and AL, in PWMCHB, controls the duty cycle of
the signals on BH and BL and in PWMCHC, controls the duty
cycle of the signals on CH and CL. The duty-cycle registers are
programmed in integer counts of the fundamental time unit,
t
produced by the three-phase timing unit over half the PWM
period. The switching signals produced by the three-phase
timing unit are also adjusted to incorporate the programmed
dead time value in the PWMDT register. The three-phase
timing unit produces active LO signals so that a LO level corre-
sponds to a command to turn on the associated power device.
A typical pair of PWM outputs (in this case for AH and AL)
from the timing unit are shown in Figure 6 for operation in
single update mode. All illustrated time values indicate the
integer value in the associated register and can be converted to
time simply by multiplying by the fundamental time increment,
t
symmetrical about the midpoint of the switching period in
this single update mode since the same values of PWMCHA,
PWMTM and PWMDT are used to define the signals in both
half cycles of the period. It can be seen how the programmed
duty cycles are adjusted to incorporate the desired dead time
into the resultant pair of PWM signals. Clearly, the dead time is
incorporated by moving the switching instants of both PWM
signals (AH and AL) away from the instant set by the PWMCHA
register. Both switching edges are moved by an equal amount
(PWMDT × t
Also shown is the PWMSYNC pulse whose width is set by the
PWMSYNCWT register and Bit 3 of the SYSSTAT register,
which indicates whether operation is in the first or second half
cycle of the PWM period.
Obviously negative values of T
the minimum permissible value is zero, corresponding to a 0%
duty cycle. In a similar fashion, the maximum value is T
corresponding to a 100% duty cycle.
CK
CK
PWMSYNC
, and define the desired on-time of the high side PWM signal
. Firstly, it is noted that the switching patterns are perfectly
, is given by:
T
PWMSYNC
CK
) to preserve the symmetrical output patterns.
= t
CK
× (PWMSYNCWT + 1)
AH
and T
AL
are not permitted and
CK
to 256 t
S
,
CK
The resultant on-times of the PWM signals in Figure 6 may be
written as:
and the corresponding duty cycles are:
The output signals from the timing unit for operation in double
update mode are shown in Figure 7. This illustrates a com-
pletely general case where the switching frequency, dead time
and duty cycle are all changed in the second half of the PWM
period. Of course, the same value for any or all of these quanti-
ties could be used in both halves of the PWM cycle. However,
it can be seen that there is no guarantee that symmetrical PWM
signal will be produced by the timing unit in this double update
mode. Additionally, it is seen that the dead time is inserted into
the PWM signals in the same way as in the single update mode.
In general, the on-times of the PWM signals in double update
mode can be defined as:
T
SYSSTAT (3)
SYSSTAT (3)
AH
PWMSYNC
PWMSYNC
= PWMCHA
– PWMDT
T
AL
(
T
AH
AL
AH
d
AL
AL
= ( PWMTM
AL
= 2 × (PWMTM–PWMCHA–PWMDT) × t
T
=
2
2
AH
d
T
1
T
AH
PWMDT
PWMDT
PWMSYNCWT
AL
– PWMDT
= 2 × (PWMCHA – PWMDT) × t
S
=
PWMTM
1
=
+ PWMCHA
PWMTM
T
1
T
PWMTM – PWMCHA – PWMDT
1
AH
+ PWMTM
S
1
PWMCHA
=
1
2
PWMCHA – PWMDT
PWMCHA
+ 1
) ×
t
CLK
1
2
2
PWMTM
− PWMDT
– PWMCHA
PWMTM
PWMCHA
PWMCHA
2
PWMTM
PWMSYNCWT
ADMC331
PWMSYNCWT + 1
1
PWMTM
1
− PWMDT
– PWMCHA
2
2
2
CK
PWMDT
PWMDT
2
CK
+ 1
2
)
2
2
× t
CK