admc331 Analog Devices, Inc., admc331 Datasheet - Page 20

• Manufacturer Part Number: admc331
• Description: Single Chip Dsp Motor Controller
• Manufacturer: Analog Devices, Inc.

ADMC331
To ensure that the full input range of the ADC is utilized, it is
necessary to select the capacitor so that at the maximum capaci-
tance value and the minimum current source output, the ramp
voltage will charge to at least 3.5 V.
As a result, assuming ± 10% variations in both the capacitance
and current source, the nominal capacitance value required at a
given PWM period is:
The largest standard value capacitor that is less than this calcu-
lated value is chosen. Table VIII shows the appropriate standard
capacitor value to use for various PWM switching frequencies
assuming ± 10% variations in both the current source and ca-
pacitor tolerances. If required, more precise control of the ramp
voltage is possible by using higher precision capacitor compo-
nents, an external current source and/or series or parallel timing
capacitor combinations.
PWM Frequency
(kHz)
MODECTRL[6] = 0
2.1–2.7
2.7–3.2
3.2–3.9
3.9–4.7
4.7–5.6
5.6–6.7
6.7–8.0
8.0–9.5
9.5–11.5
11.5–14.1
14.1–17.1
17.1–20.4
20.4–25.3
25.3–30.1
ADC Registers
The configuration of all registers of the ADC System is shown
at the end of the data sheet.
AUXILIARY PWM TIMERS
Overview
The ADMC331 provides two variable-frequency, variable duty
cycle, 8-bit, auxiliary PWM outputs that are available at the
AUX1 and AUX0 pins. These auxiliary PWM outputs can be
used to provide switching signals to other circuits in a typical
motor control system such as power factor corrected front-end
converters or other switching power converters. Alternatively,
by addition of a suitable filter network, the auxiliary PWM out-
put signals can be used as simple single-bit digital-to-analog
converters.
The auxiliary PWM system of the ADMC331 can operate in
two different modes, independent mode or offset mode. The
operating mode of the auxiliary PWM system is controlled
by Bit 8 of the MODECTRL register. Setting Bit 8 of the
MODECTRL register places the auxiliary PWM system in the
Table VIII. Timing Capacitor Selection
C
NOM
=
(0.9 × I
PWM Frequency
(kHz)
MODECTRL[6] = 1
4.2–5.2
5.2–6.3
6.3–7.7
7.7–9.2
9.2–11.2
11.2–13.3
13.3–16.0
16.0–18.8
18.8–23.0
23.0–28.1
28.1–34.1
34.1–40.8
40.8–50.6
50.6–60.2
CONST
(1.1)(3.5)
)(T
PWM
– T
CRST
)
Timing
Capacitor
(pF)
1500
1200
1000
820
680
560
470
390
330
270
220
180
150
120
independent mode. In this mode, the two auxiliary PWM gen-
erators are completely independent and separate switching fre-
quencies and duty cycles may be programmed for each auxiliary
PWM output. In this mode, the 8-bit AUXTM0 register sets
the switching frequency of the signal at the AUX0 output pin.
Similarly, the 8-bit AUXTM1 register sets the switching of the
signal at the AUX1 pin. The fundamental time increment for
the auxiliary PWM outputs is twice the DSP instruction rate (or
2 t
Since the values in both AUXTM0 and AUXTM1 can range
from 0 to 0xFF, the achievable switching frequency of the auxil-
iary PWM signals may range from 50.8 kHz to 13 MHz for a
CLKOUT frequency of 26 MHz.
The on-time of the two auxiliary PWM signals is programmed
by the two 8-bit AUXCH0 and AUXCH1 registers, according
to:
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 13(a).
When Bit 8 of the MODECTRL register is cleared, the auxiliary
PWM channels are placed in offset mode. In offset mode, the
switching frequency of the two signals on the AUX0 and AUX1
pins are identical and controlled by AUXTM0 in a manner
similar to that previously described for independent mode. In
addition, the on times of both the AUX0 and AUX1 signals are
controlled by the AUXCH0 and AUXCH1 registers as before.
However, in this mode the AUXTM1 register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:
For correct operation in this mode, the value written to the
AUXTM1 register must be less than the value written to the
AUXTM0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 13(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is 8-bit only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
= 255 in offset mode). Obviously as the switching frequency is
increased the resolution is reduced.
Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the AUXCH0
and AUXCH1 registers only become effective at the start of the
next cycle. Writing to the AUXTM0 or AUXTM1 registers
cause the internal timers to be reset to 0 and new PWM cycles
begin.
By default, following power on or a reset, Bit 8 of the
MODECTRL register is cleared so that offset mode is enabled.
In addition, the registers AUXTM0 and AUXTM1 default to
0xFF, corresponding to minimum switching frequency and zero
offset. In addition, the on-time registers AUXCH0 and AUXCH1
default to 0x00.
CK
) so that the corresponding switching periods are given by:
T
T
T
T
T
OFFSET
AUX1
AUX0
ON
ON
,
,
AUX0
AUX1
= 2 × (AUXTM0 + 1) × t
= 2 × (AUXTM1 + 1) × t
= 2 × (AUXTM1 + 1) × t
= 2 × (AUXCH0) × t
= 2 × (AUXCH1) × t
CK
CK
CK
CK
CK