admc331 Analog Devices, Inc., admc331 Datasheet - Page 14

• Manufacturer Part Number: admc331
• Description: Single Chip Dsp Motor Controller
• Manufacturer: Analog Devices, Inc.

ADMC331
These registers, in conjunction with the three 16-bit duty-cycle
registers (PWMCHA, PWMCHB and PWMCHC), control the
output of the three-phase timing unit.
PWM Switching Frequency, PWMTM Register
The PWM switching frequency is controlled by the 16-bit read/
write PWM period register, PWMTM. The fundamental timing
unit of the PWM controller is t
Therefore, for a 26 MHz CLKOUT, the fundamental time
increment is 38.5 ns. The value written to the PWMTM regis-
ter is effectively the number of t
PWM period. The required PWMTM value is a function of the
desired PWM switching frequency (f
Therefore, the PWM switching period, T
For example, for a 26 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
to load into the PWMTM register is:
The largest value that can be written to the 16-bit PWMTM
register is 0xFFFF = 65,535 which corresponds to a minimum
PWM switching frequency of:
PWM Switching Dead Time, PWMDT Register
The second important parameter that must be set up in the
initial configuration of the PWM block is the switching dead
time. That is a short delay time introduced between turning off
one PWM signal (AH) and turning on the complementary sig-
nal, AL. This short time delay is introduced to permit the
power switch being turned off (AH in this case) to completely
recover its blocking capability before the complementary switch
is turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link ca-
pacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write PWMDT
register. There is only one dead time register that controls the
dead time inserted into the three pairs of PWM output signals.
The dead time, T
ter by:
Therefore, a PWMDT value of 0x00A (= 10), introduces a
769.2 ns delay between the turn-off on any PWM signal (AH)
and the turn-on of its complementary signal (AL). The amount
of the dead time can therefore be programmed in increments of
2 t
register is a 10-bit register so that its maximum value is 0x3FF
CK
(or 76.92 ns for a 26 MHz CLKOUT). The PWMDT
f
PWM, min
PWMTM =
PWMTM =
D
, is related to the value in the PWMDT regis-
T
T
D
S
= 2 × PWMTM × t
= PWMTM × 2 × t
=
2 × 65,535
26 ×10
2 × f
2 ×10 ×10
f
26 ×10
CLKOUT
CK
CK
S
PWM
clock increments in half a
6
= 100 µs), the correct value
(DSP instruction rate).
PWM
= 198.4 Hz
6
=
3
) and is given by:
S
f
= 1300
, can be written as:
CK
f
CK
CLKIN
PWM
(=1023) corresponding to a maximum programmed dead time
of:
for a CLKOUT rate of 26 MHz. Obviously, the deadtime can
be programmed to be zero by writing 0 to the PWMDT register.
PWM Operating Mode, MODECTRL and SYSSTAT Registers
The PWM controller of the ADMC331 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power on, Bit 6 of the
MODECTRL register is cleared so that the default operating
mode is in single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle and is used to latch new values from
the PWM configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) and the PWM duty-cycle registers
(PWMCHA, PWMCHB and PWMCHC) into the three-phase
timing unit. In addition, the PWMSEG register is also latched
into the output control unit on the rising edge of the PWMSYNC
pulse. In effect, this means that the characteristics and resultant
duty cycles of the PWM signals can be updated only once per
PWM period at the start of each cycle. The result is that PWM
patterns that are symmetrical about the midpoint of the switch-
ing period are produced.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The rising
edge of this new PWMSYNC pulse is again used to latch new
values of the PWM configuration registers, duty-cycle registers
and the PWMSEG register. As a result it is possible to alter
both the characteristics (switching frequency, dead time, minimum
pulsewidth and PWMSYNC pulsewidth) as well as the output
duty cycles at the midpoint of each PWM cycle. Consequently, it is
possible to produce PWM switching patterns that are no longer
symmetrical about the midpoint of the period (asymmetrical
PWM patterns).
In the double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 3 of the SYSSTAT register, which is cleared during opera-
tion in the first half of each PWM period (between the rising
edge of the original PWMSYNC pulse and the rising edge of
the new PWMSYNC pulse introduced in double update mode).
Bit 3 of the SYSSTAT register is set during operation in the
second half of each PWM period. This status bit allows the user
to make a determination of the particular half-cycle during
implementation of the PWMSYNC interrupt service routine, if
required.
The advantage of the double update mode is that lower har-
monic voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Since new duty cycle values
must be computed in each PWMSYNC interrupt service rou-
tine, there is a larger computational burden on the DSP in the
double update mode.
T
D,max
= 1023 × 2 × t
CK
= 1023 × 2 × 38.46 × 10
–9
= 78.69 µ s