xc4000a Xilinx Corp., xc4000a Datasheet - Page 4

• Manufacturer Part Number: xc4000a
• Description: Logic Cell Array Family
• Manufacturer: Xilinx Corp.

XC4000A Logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
T going High to TBUF going inactive, not driving L.L.
T going High to L.L. going from Low to High,
pulled up by a single resistor
T going High to L.L. going from Low to High,
pulled up by two resistors
2-74
Symbol
T
T
T
T
T
T
OFF
PUS
PUF
IO1
IO2
ON
Speed Grade
All devices
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
Device
Max
10.0
10.5
10.1
10.7
11.4
12.0
23.0
24.0
25.0
26.0
10.5
11.0
11.5
12.0
-6
8.2
8.8
9.4
8.7
9.3
9.9
3.0
Max
10.0
19.0
20.0
21.0
22.0
10.0
-5
6.0
6.2
6.6
7.0
6.5
6.7
7.1
7.5
8.4
9.0
9.5
2.0
8.5
9.0
9.5
Max
14.0
16.0
4.4
5.5
5.0
6.0
7.2
8.0
1.8
7.0
8.0
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns