xc4000a Xilinx Corp., xc4000a Datasheet - Page 6

• Manufacturer Part Number: xc4000a
• Description: Logic Cell Array Family
• Manufacturer: Xilinx Corp.

XC4000A Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
Description
Propagation Delays
Set-up Time (Note 3)
Hold Time (Note 3)
OUTPUT
Propagation Delays
Additional Delay
Set-up and Hold Times
Clock
Global Set/Reset
INPUT
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
Clock (OK) to Pad (fast)
Output (O) to Pad (fast)
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
For medium fast outputs
For medium slow outputs
For slow outputs
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock High or Low time
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
2-76
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PID
PLI
PDLI
IKRI
IKLI
PICK
PICKD
IKPI
IKPID
OKPOF
OPF
TSHZ
TSONF
OOK
OKO
CH/
RRI
RPO
MRW
T
CL
Min Max
25.0
21.0
neg
7.0
1.0
8.0
0.0
5.0
-6
26.0
13.0
14.5
18.0
4.0
8.0
8.0
8.0
7.5
9.0
9.0
2.0
4.0
6.0
24 .0
Min Max
18.0
neg
6.0
1.0
6.0
0.0
4.0
-5
24.0
10.0
13.5
17.0
3.0
7.0
7.0
7.0
7.0
7.0
7.0
1.5
3.0
4.5
Min Max Units
18.0
4.0
neg
XC4003A
XC4005A
1.0
5.5
0
4.0
**
-4
13.5
14.6
2.8
6.0
6.0
6.0
6.5
5.5
6.5
9.5
1.0
2.0
3.0
**
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns