xc4000h Xilinx Corp., xc4000h Datasheet
xc4000h
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xc4000h Summary of contents
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... XC4000-family devices have generous routing resources to accommodate the most complex interconnect patterns. XC4000A devices have reduced sets of routing resources, sufficient for their smaller size. XC4000H high I/O devices maintain the same routing resources and CLB structure as the XC4000 family, while nearly doubling the available I/O. ...
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... IOB has Longline access through its own TBUF. Outputs are n-channel only, lower V XC4000 outputs can be paired to double sink current to 24 mA. XC4000A and XC4000H outputs can each sink 24 mA, can be paired for 48 mA sink current. IEEE 1149.1- type boundary scan is supported in the I/O. ...
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Architectural Overview The XC4000 families achieve high speed through ad- vanced semiconductor technology and through improved architecture, and supports system clock rates MHz. Compared to older Xilinx FPGA families, the XC4000 families are more powerful, offering ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families G4 G3 LOGIC FUNCTION G' OF G1- LOGIC FUNCTION OF F', G', AND LOGIC FUNCTION F' OF F1- (CLOCK) Figure 1. Simplified Block Diagram of XC4000-Families Configurable Logic Block independently for each of the two registers; this input also can be disabled for either flip-flop. A separate global Set/ ...
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Speed Is Enhanced Two Ways Delays in LCA-based designs are layout dependent. While this makes it hard to predict a worst-case guaranteed performance, there is a rule of thumb designers can consider — the system clock rate should not exceed ...
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... Two adjacent outputs may be intercon- nected to increase the output sink current to 24 mA. The FPGA can thus drive short buses board. The Logic XC4000A and XC4000H outputs can sink 24 mA per Function output and can double up for 48 mA. ...
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... On-Chip Memory The XC4000, XC4000A and XC4000H family devices are the first programmable logic devices with RAM accessible to the user. An optional mode for each CLB makes the memory look- ...
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... Each XC4000-families output buffer is capable of sinking 12 mA; two adjacent output buffers can be wire-ANDed externally to sink mA. In the XC4000A and XC4000H families, each output buffer can sink 24 mA. There are a number of other programmable options in the IOB. Programmable pull-up and pull-down resistors are ...
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CLB in the array. Each Switch Matrix consists of programmable n-channel pass transistors used to establish connections between the single-length lines (Figure 7). For example, a signal entering on the right side of the Switch Matrix can be ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Communication between Longlines and single-length lines is controlled by programmable interconnect points at the line intersections. Double-length lines do not connect to other lines. Three-State Buffers A pair of 3-state buffers, associated with each CLB in the array, can be used to drive signals onto the nearest horizontal Longlines above and below the block ...
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I/O functions, latches, Boolean functions, RAM and ROM memory blocks, multiplexers, shift registers, and barrel shifters. Designing with macros is as easy as designing with standard SSI/MSI functions. The ‘soft macro’ library con- ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families The XACT system also includes XDelay, a static timing analyzer. XDelay examines a design’s logic and timing to calculate the performance along signal paths, identify pos- sible race conditions, and detect set-up and hold-time violations. Timing analyzers do not require that the user generate input stimulus patterns or test vectors ...
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... Independent of this choice, each IOB has a pull- up resistor during the configuration process. The 3-state output driver uses a totem pole n-channel output structure. V than V CC symmetrical. Family XC4000 XC4000A XC4000H *XC4000H devices can sink only 4 mA configured for SoftEdge mode EXTEST TS INV capture Boundary Scan TS - update ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families The inputs drive TTL-compatible buffers with 1.2-V input threshold and a slight hysteresis of about 300 mV. These buffers drive the internal logic as well as the D-input of the input flip-flop. Under configuration control, the set-up time of this flip-flop can be increased so that normal clock routing does not result in a hold-time problem ...
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G4 G3 LOGIC FUNCTION G' OF G1- FUNCTION F4 F3 LOGIC FUNCTION F' OF F1- (CLOCK) Figure 13. Simplified Block Diagram of XC4000 Configurable Logic Block Carry Logic CIN ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Boundary Scan Boundary Scan is becoming an attractive feature that helps sophisticated systems manufacturers test their PC boards more safely and more efficiently. The XC4000 family implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST Boundary-Scan instruc- tions. When the Boundary-Scan configuration option is selected, three normal user I/O pins become dedicated inputs for these functions ...
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IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER IOB INSTRUCTION REGISTER TDI M U TDO X INSTRUCTION REGISTER IOB BYPASS REGISTER IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB Figure 16. XC4000 Boundary Scan ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Interconnects The XC4000 families use a hierarchy of interconnect resources. • General purpose single-length and double-length lines offer fast routing between adjacent blocks, and highest flexibility for complex routes, but they incur a delay every time they pass through a switch matrix. ...
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Oscillator An internal oscillator is used for clocking of the power-on time-out, configuration memory clearing, and as the source of CCLK in Master modes. This oscillator signal runs at a nominal 8 MHz and varies with process, V temperature between ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families 11111111 0010 < 24-BIT LENGTH COUNT > 1111 0 < DATA FRAME # 001 > eeee 0 < DATA FRAME # 002 > eeee 0 < DATA FRAME # 003 > eeee . . . . . . . . . . . . 0 < DATA FRAME # N-1 > eeee 0 < DATA FRAME # N > eeee 0111 1111 Device XC4002A XC4003A XC4003/H XC4004A XC4005A XC4005/H XC4006 ...
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Boundary Scan >3.5 V Instructions Available: Yes Test M0 Generate One Time-Out Pulse Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families tion data bits and a 4-bit frame error field frame data error is detected, the LCA device halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an LCA device, DOUT again follows the input data so that the remaining data is passed on to the next device ...
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Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000 CCLK_NOSYNC GSR Active DONE I/O XC4000 CCLK_SYNC GSR Active DONE I/O XC4000 UCLK_NOSYNC GSR Active DONE I/O XC4000 UCLK_SYNC GSR Active Synchronization Uncertainty ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Q3 Q1/Q4 STARTUP DONE FULL S Q LENGTH COUNT K CLEAR MEMORY CCLK 0 STARTUP.CLK 1 USER NET M * Figure 22. Start-up Logic All Xilinx FPGAs of the XC2000, XC3000, XC4000 familiies use a compatible bitstream format and can, therefore, be connected in a daisy-chain in an arbitrary sequence. There is however one limitation ...
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Reset Active Low Output 1 1 Active High Output etc . . . . the extra CCLK pulse. This solution requires one CLB, one IOB and pin, and an internal oscillator with ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Master Serial Mode GENERAL- PURPOSE USER I/O PINS PROGRAM In Master Serial mode, the CCLK output of the lead LCA device drives a Xilinx Serial PROM that feeds the LCA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter ...
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A master device waits an additional Master Serial Mode Programming Switching Characteristics CCLK (Output DSCK Serial Data In ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Slave Serial Mode MICRO COMPUTER STRB D0 D1 I/O D2 PORT RESET In Slave Serial mode, an external signal drives the CCLK input(s) of the LCA device(s). The serial configuration bitstream must be available at the DIN input of the lead LCA device a short set-up time before each rising CCLK edge ...
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Slave Serial Mode Programming Switching Characteristics DIN 1 T DCC CCLK DOUT (Output) Description CCLK DIN setup DIN hold to DOUT High time Low time Frequency Note: Configuration must be delayed until the INIT of all daisy-chained LCA devices is ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Master Parallel Mode M0 DOUT HDC LDC GENERAL- PURPOSE RCLK RCLK USER I/O PINS INIT OTHER I/O PINS PROGRAM PROGRAM Master Parallel mode, the lead LCA device directly ad- dresses an industry-standard byte-wide EPROM, and ac- cepts eight data bits right before incrementing (or decrementing) the address outputs ...
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Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration, causes the LCA device to wait after having completed the configuration memory clear operation. When INIT is no longer held Low externally, the device determines ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Synchronous Peripheral Mode CLOCK DATA BUS CONTROL SIGNALS REPROGRAM Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the LCA device(s). The first byte of parallel configuration data must be available at the D inputs of the lead LCA device a short set-up time before the rising CCLK edge ...
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Synchronous Peripheral Mode Programming Switching Characteristics CCLK INIT BYTE 0 DOUT RDY/BUSY Description CCLK INIT (High) Setup time required D0-D7 Setup time required D0-D7 Hold time required CCLK High time CCLK Low time CCLK Frequency Notes: Peripheral Synchronous mode can ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Asynchronous Peripheral Mode DATA BUS +5 V ADDRESS BUS CONTROL SIGNALS REPROGRAM Write to LCA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1 and WS inputs to accept byte-wide data from a microprocessor bus. In the ...
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A Low on the PROGRAM input is the more radical ap- proach, and is recommended when the power-supply rise time is excessive or poorly defined. As long as PROGRAM is Low, the XC4000 device keeps clearing its configuration memory. When ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families General LCA Switching Characteristics Vcc PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes Power-On-Reset M0 = High M0 = Low Program Latency CCLK (output) Delay period (slow) period (fast) Slave and Peripheral Modes Power-On-Reset Program Latency ...
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CONFIGURATION MODE: <M2:M1:M0> MASTER-SER SLAVE <0:0:0> <1:1:1> TDI TDI TCK TCK TMS TMS M1 (HIGH) (I) M1 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) M2 (LOW) (I) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) INIT-ERROR ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins V CC Eight or more (depending on package type) connections to the nominal +5 V supply voltage. All must be connected. GND Eight or more (depending on package type) connections to ground. All must be connected. CCLK During configuration, Configuration Clock is an output of ...
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HDC High During Configuration is driven High until configura- tion is completed available as a control output indicat- ing that configuration is not yet completed. After configu- ration, this is a user-programmable I/O pin. LDC Low During Configuration ...
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... XC4000, XC4000A, XC4000H Logic Cell Array Families For a detailed description of the device architecture, see page 2-9 through 2-31. For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55. For detailed lists of package pinouts, see pages 2-57 through 2-67, 2-70, 2-81 through 2-85, and 2-100 through 2-101. ...