xc4000h Xilinx Corp., xc4000h Datasheet - Page 31

• Manufacturer Part Number: xc4000h
• Description: Logic Cell Array Families
• Manufacturer: Xilinx Corp.

Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
externally, the device determines its configuration mode by
Master Parallel Mode Programming Switching Characteristics
Notes: 1. At power-up, V
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
RCLK
(output)
(output)
(output)
(output)
A0-A17
D0-D7
DOUT
RCLK
CCLK
2. Configuration can be delayed by holding INIT Low with or until after the INIT of all daisy-chain slave mode devices
3. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
until V
is High.
CC
is valid.
CC
must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration using PROGRAM
Description
Delay to Address valid
Data setup time
Data hold time
Address for Byte n
2-37
7 CCLKs
1
2
3
Symbol
capturing its status inputs, and is ready to start the configura-
tion process. A master device waits an additional max 250 s
to make sure that all slaves in the potential daisy-chain have
seen INIT being High.
T
T
T
RAC
DRC
RCD
2 T
Byte
DRC
Byte n - 1
Min
60
D6
0
0
Address for Byte n + 1
1 T
3 T
CCLK
RAC
RCD
Max
200
D7
Units
X6078
ns
ns
ns