xa3s100e Xilinx Corp., xa3s100e Datasheet - Page 30
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xa3s100e
Manufacturer Part Number
xa3s100e
Description
Xa Spartan-3e Automotive Fpga Family Data Sheet
Manufacturer
Xilinx Corp.
Datasheet
1.XA3S100E.pdf
(36 pages)
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Configuration Clock (CCLK) Characteristics
Table 35: Master Mode CCLK Output Period by ConfigRate Option Setting
Table 36: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Table 37: Master Mode CCLK Output Minimum Low and High Time
Table 38: Slave Mode CCLK Input Low and High Time
DS635 (v1.1) January 20, 2009
Product Specification
Notes:
1.
T
T
T
T
T
T
F
F
F
F
F
F
T
T
T
T
Symbol
Symbol
Symbol
Symbol
CCLK1
CCLK3
CCLK6
CCLK12
CCLK25
CCLK50
CCLK1
CCLK3
CCLK6
CCLK12
CCLK25
CCLK50
MCCL,
MCCH
SCCL,
SCCH
Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in DS312, Module 2.
R
CCLK Low and High time
Master mode CCLK minimum
Low and High time
CCLK clock period by
ConfigRate setting
Equivalent CCLK clock
frequency by ConfigRate
setting
Description
Description
Description
Description
(power-on value)
(power-on value)
Q-Grade
I-Grade
ConfigRate
ConfigRate
Setting
Setting
12
25
50
12
25
50
1
3
6
1
3
6
www.xilinx.com
235
1
Temperature
Temperature
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
Q-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
I-Grade
Range
Range
117
3
ConfigRate Setting
58
6
Minimum
Minimum
60.6
30.3
15.1
12.8
25.6
485
242
121
0.8
1.6
3.2
6.4
29.3
12
Min
5
14.5
25
Maximum
Maximum
1,250
78.2
39.1
16.5
33.0
66.0
625
313
157
Max
2.1
4.2
8.3
∞
7.3
50
Units
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
Units
ns
ns
ns
ns
ns
ns
ns
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