xa3sd3400a Xilinx Corp., xa3sd3400a Datasheet

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... Rows Columns XA3SD1800A 1800K 37,440 88 XA3SD3400A 3400K 53,712 104 Notes convention, one Kb is equivalent to 1,024 bits. © 2008–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries ...

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... IOBs surrounds a regular array of CLBs. The XA3SD1800A has four columns of DSP48A slices, and the XA3SD3400A has five columns of DSP48A slices. Each DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the columns of block RAM and DSP48As ...

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... The XA3SD1800A and XA3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer block RAM/DSP48A columns of the columns in the selected device, as shown in the diagram above. ...

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... CSG484 User Diff 309 140 (60) (78) 309 140 (60) (78) required for creating a production configuration bitstream. Later versions are also supported. I-Grade Standard (-4) Production XA3SD1800A (v1.32) Production XA3SD3400A (v1.32) www.xilinx.com FGG676 User Diff 519 227 (110) (131) 469 213 (60) (117) Q-Grade Standard (-4) Production (v1.32) - ...

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... Speed Grade XA3SD1800A -4 Standard Performance XA3SD3400A Notes: 1. The XA Spartan-3A DSP FPGA product line is available in -4 speed grade only. 2. The XA3SD3400A is available in I-Grade only. DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet BGA Ball A1 R SPARTAN R XA3SD1800A Device Type ...

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R DC Electrical Characteristics All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply to all XA Spartan-3A DSP devices. AC and DC characteristics are specified using the same ...

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R Power Supply Specifications Table 5: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes and V supplies ...

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R General Recommended Operating Conditions Table 8: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2) V Input voltage IN T Input ...

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R General DC Characteristics for I/O Pins Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered Leakage current on pins during ...

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... XA Spartan-3A DSP Automotive FPGA Family Data Sheet Device Typical XA3SD1800A 41 XA3SD3400A 64 XA3SD1800A 0.4 XA3SD3400A 0.4 XA3SD1800A 25 XA3SD3400A 39 Table 8. = 1.26V 3.6V, and V = 3.6V. The FPGA is programmed with a “blank” configuration data CCO CCAUX provides quick, approximate, typical estimates, and does not require a netlist of the design. www.xilinx.com I-Grade Q-Grade ...

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R Single-Ended I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V IOSTANDARD CCO Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 (4) LVCMOS18 1.65 (4) LVCMOS15 1.4 (4) LVCMOS12 1.1 ...

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R Table 12: DC Characteristics of User I/Os Using Single- Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – –12 16 ...

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R Differential I/O Standards X-Ref Target - Figure 3 Internal Logic GND level Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 (3) LVDS_33 3.0 (4) BLVDS_25 2.25 ...

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R X-Ref Target - Figure 4 Internal Logic V OUTN V OUTP GND level Table 14: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 300 RSDS_25 ...

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R External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards X-Ref Target - Figure 3. 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only differential pairs or ...

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... DS705 (v1.1) January 20, 2009 Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet Table 16: XA Spartan-3A DSP FPGA v1.32 Speed Grade Designations XA3SD1800A XA3SD3400A Table 17 provides the recent history of the XA Spartan-3A DSP FPGA speed files. Table 17: XA Spartan-3A DSP Speed File Version History Version 1 ...

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... XA3SD3400A (4) with DCM (2) LVCMOS25 , XA3SD1800A IFD_DELAY_VALUE = 6, XA3SD3400A without DCM (3) LVCMOS25 , XA3SD1800A IFD_DELAY_VALUE = 0, XA3SD3400A (4) with DCM (3) LVCMOS25 , XA3SD1800A IFD_DELAY_VALUE = 6, XA3SD3400A without DCM Table 27 and are based on the operating conditions set forth in Table 23. If this is true of the data Input, add the Table 23. If this is true of the data Input, subtract the www ...

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... Product Specification XA Spartan-3A DSP Automotive FPGA Family Data Sheet IFD_DELAY_ Conditions Device VALUE (2) LVCMOS25 0 XA3SD1800A XA3SD3400A (2) LVCMOS25 1 XA3SD1800A XA3SD3400A (2) LVCMOS25 0 XA3SD1800A XA3SD3400A www.xilinx.com Speed Grade -4 Units Min 1.81 ns 1.88 ns 2.24 ns 2.83 ns 3.64 ns 4.20 ns 4.16 ns 5.09 ns 6.02 ns 6.63 ns 2.44 ns 3.02 ns 3.81 ns 4. ...

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... When the hold time is negative possible to change the data before the clock’s active Max 30879 www.xilinx.com Speed Grade -4 Device VALUE Min 1 XA3SD1800A -1.40 2 -2.11 3 -2.48 4 -2.77 5 -2.62 6 -3.06 7 -3.42 8 -3.65 1 XA3SD3400A -1.31 2 -1.88 3 -2.44 4 -2.89 5 -2.83 6 -3.33 7 -3.63 8 -3.96 - All 1.61 and are based on the operating conditions set forth in Units ...

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... Conditions _VALUE (2) LVCMOS25 0 (2) LVCMOS25 Table 27 and are based on the operating conditions set forth in Table 23. www.xilinx.com Speed Grade Device -4 Units Max XA3SD1800A 2.04 ns XA3SD3400A 2.11 ns XA3SD1800A 2.47 ns 3.06 ns 3.86 ns 4.43 ns 4.39 ns 5.32 ns 6.24 ns 6.86 ns XA3SD3400A 2.67 ns 3.25 ns 4.04 ns 4.62 ns 4.49 ns 5.31 ns 6. ...

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R Input Timing Adjustments Table 23: Input Timing Adjustments by IOSTANDARD Convert Input Time from Adjustment LVCMOS25 to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I ...

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R Output Propagation Times Table 24: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output Flip-Flop IOCKP (OFF), the time from the active transition at the OCLK input to data appearing at the ...

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R Three-State Output Propagation Times Table 25: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK input IOCKHZ of the Three-state Flip-Flop (TFF) to when the Output pin ...

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R Output Timing Adjustments Table 26: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...

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R Table 26: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow ...

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R Table 26: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 PPDS_25 PPDS_33 ...

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R Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 27 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A ...

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R Table 27: Test Methods for Timing Measurement at I/Os (Cont’d) Signal Standard (IOSTANDARD) V REF Differential LVDS_25 - LVDS_33 - BLVDS_25 - MINI_LVDS_25 - MINI_LVDS_33 - LVPECL_25 - LVPECL_33 - RSDS_25 - RSDS_33 - TMDS_33 - PPDS_25 - PPDS_33 ...

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... FPGAs mounted in sockets, due to the lead inductance introduced by the socket. (Table 26) to The SSO values assume that the V 3.3V. Setting V characteristics. Table 28: Equivalent V Device XA3SD1800A XA3SD3400A CCO Table 28 www.xilinx.com /GND pairs. The CCO Table 29 /GND pair within an CCO Table 29 are categorized by ...

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R Table 29: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (V CCO Signal Standard (IOSTANDARD) Top, Bottom (Banks 0,2) Single-Ended Standards Slow 2 LVTTL Fast ...

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R Table 29: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (V CCO Signal Standard (IOSTANDARD) Top, Bottom (Banks 0,2) Slow 2 LVCMOS15 Fast QuietIO ...

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R Configurable Logic Block Timing Table 30: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time from the active CKO transition at the CLK input to data appearing at the XQ (YQ) output ...

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R Table 31: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on the distributed RAM SHCKO output Setup Times T Setup time of data at the BX ...

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R Clock Buffer/Multiplexer Switching Characteristics Table 33: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input ...

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R Block RAM Timing Table 34: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the active transition at the CLK input to data RCKO_DOA_NC appearing at the DOUT output T Clock CLK to ...

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R DSP48A Timing To reference the DSP48A block diagram, see the XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide (UG431). Table 35: Setup Times for the DSP48A Symbol Description Setup Times of Data/Control Pins to the Input Register Clock T ...

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R Table 36: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A Symbol Description Clock to Out from Output Register Clock to Output Pin T CLK (PREG output DSPCKO_PP Clock to Out from Pipeline Register Clock ...

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R Digital Clock Manager Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. ...

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R Table 38: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV Frequency for the ...

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R Digital Frequency Synthesizer Table 39: Recommended Operating Conditions for the DFS Symbol (2) Input Frequency Ranges F CLKIN_FREQ_FX Frequency for the CLKIN input CLKIN (3) Input Clock Jitter Tolerance CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX ...

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R Phase Shifter Table 41: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Operating Frequency Ranges PSCLK_FREQ (F ) Frequency for the PSCLK input PSCLK Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the ...

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R DNA Port Timing Table 44: DNA_PORT Interface Timing Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before ...

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R Suspend Mode Timing X-Ref Target - Figure 9 Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 45: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of ...

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R Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing X-Ref Target - Figure 10 V CCINT (Supply) V CCAUX (Supply) V Bank 2 CCO (Supply) PROG_B (Input) INIT_B (Open-Drain) CCLK (Output) Notes: 1. The and V ...

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R Configuration Clock (CCLK) Characteristics Table 47: CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T CCLK1 ConfigRate setting T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T CCLK12 T CCLK13 T CCLK17 ...

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R Table 48: CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F CCLK1 by ConfigRate setting F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 F CCLK17 F CCLK22 F ...

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R Slave Serial Mode Timing X-Ref Target - Figure 11 PROG_B (Input) INIT_B (Open-Drain) CCLK (Input) DIN (Input) DOUT (Output) Figure 11: Waveforms for Slave Serial Configuration Table 51: Timing for the Slave Serial Configuration Modes Symbol Clock-to-Output Times T ...

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R Slave Parallel Mode Timing X-Ref Target - Figure 12 PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK ...

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R Serial Peripheral Interface Configuration Timing X-Ref Target - Figure 13 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK ...

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R Table 54: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH ...

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R Byte Peripheral Interface Configuration Timing X-Ref Target - Figure 14 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK ...

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R Table 56: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR Flash PROM ...

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R IEEE 1149.1/1553 JTAG Test Access Port Timing X-Ref Target - Figure 15 TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 57: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition ...

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R Revision History The following table shows the revision history for this document: Date Version 07/10/08 1.0 Initial Xilinx release. • Updated 01/20/09 1.1 • Removed MultiBoot description from • Updated Note 2 in • Updated T Notice of Disclaimer ...