xa3sd3400a Xilinx Corp., xa3sd3400a Datasheet - Page 41

• Manufacturer Part Number: xa3sd3400a
• Description: Xa Spartan-3a Dsp Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Phase Shifter
Table 41: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 42: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
Miscellaneous DCM Timing
Table 43: Miscellaneous DCM Timing
DS705 (v1.1) January 20, 2009
Product Specification
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Operating Frequency Ranges
PSCLK_FREQ (F
Input Pulse Requirements
PSCLK_PULSE
DCM_RST_PW_MIN
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
Symbol
R
Symbol
(2)
PSCLK
)
Minimum guaranteed delay for variable phase shifting
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
Minimum duration of a RST pulse width
Description
Description
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Description
Table
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
38.
CLKIN
CLKIN < 60 MHz
Table 8
≥
60 MHz
and
Table
±[INTEGER(10 • (T
±[INTEGER(15 • (T
41.
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
Phase Shift Amount
±[MAX_STEPS •
±[MAX_STEPS •
Min
3
40%
Min
Speed Grade
1
CLKIN
CLKIN
-4
Max
-
Max
60%
167
– 3 ns))]
– 3 ns))]
CLKIN
cycles
Units
Units
MHz
Units
steps
-
ns
ns
41