xa3sd3400a Xilinx Corp., xa3sd3400a Datasheet - Page 47

• Manufacturer Part Number: xa3sd3400a
• Description: Xa Spartan-3a Dsp Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Slave Serial Mode Timing
X-Ref Target - Figure 11
Table 51: Timing for the Slave Serial Configuration Modes
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
(Open-Drain)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
CCO
DCC
CCD
CCH
CCL
CCSER
Symbol
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
(Input)
CCLK
DOUT
DIN
R
The time from the falling transition on the CCLK pin to data appearing at the DOUT pin
The time from the setup of data at the DIN pin to the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK
input pin
Figure 11: Waveforms for Slave Serial Configuration
T
DCC
Description
Bit 0
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With bitstream compression
T
CCD
Bit 1
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table
8.
T
T
MCCL
SCCL
Bit n
1/F
CCSER
T
CCO
Bit n-64
Bit n+1
Min
1.5
1.0
T
T
7
0
0
SCCH
MCCH
See
See
Bit n-63
Table 50
Table 50
Max
100
100
10
-
-
DS705_12_062308
Units
MHz
MHz
ns
ns
ns
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