ade7566acpzf8-rl Analog Devices, Inc., ade7566acpzf8-rl Datasheet - Page 127

• Manufacturer Part Number: ade7566acpzf8-rl
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 141. Serial Port Buffer SFR (SBUF, Address 0x99)
Bit
[7:0]
Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E)
Bit
7
6
5
[4:3]
[2:0]
Table 143. UART Timer Fractional Divider SFR (SBAUDF, Address 0x9D)
Bit
7
6
[5:0]
Mnemonic
UARTBAUDEN
SBAUDF
Mnemonic
OWE
FE
BE
SBTH
DIV
Mnemonic
SBUF
Default
0
0
Default
0
0
0
0
0
Description
Overwrite error. This bit is set when new data is received and RI = 1 (Bit 0 in the SCON SFR, Address
0x98). It indicates that SBUF was not read before the next character was transferred in, causing the
prior SBUF data to be lost. Write a 0 to this bit to clear it.
Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read
only and updated every time a frame is received.
Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission
frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This
bit is updated every time a frame is received.
Extended divider ratio for baud rate setting as shown in Table 144.
Binary divider. See Table 144.
DIV[2:0]
000
001
010
011
100
101
110
111
Description
UART baud rate enable. Set to enable UART timer to generate the baud rate. When set, the SMOD
bit (PCON[7]), the TCLK bit (T2CON[4]), and the RCLK bit (T2CON[5]) are ignored.
Cleared to let the baud rate be generated as per a standard 8052.
Not implemented, write don’t care.
UART timer fractional divider Bit 5.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Default
0
Result
Divide by 1.
Divide by 2.
Divide by 4.
Divide by 8.
Divide by 16.
Divide by 32.
Divide by 64.
Divide by 128.
Rev. B | Page 127 of 152
Description
Serial port data buffer.