ade7566acpzf8-rl Analog Devices, Inc., ade7566acpzf8-rl Datasheet - Page 33
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ade7566acpzf8-rl
Manufacturer Part Number
ade7566acpzf8-rl
Description
Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADE7566ACPZF8-RL.pdf
(152 pages)
- Current page: 33 of 152
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POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply monitor interrupt alerts the 8052 core of
power supply events. The PSM interrupt is disabled by default.
Setting the EPSM bit in the interrupt enable and Priority 2 SFR
(IEIP2, Address 0xA9) enables the PSM interrupt (see Table 80).
*NOT AVAILABLE IN THE ADE7116.
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN.
EVDCIN
FVDCIN
EVADC
FVADC
ESAG
FSAG
EBSO
FBSO
EPSR
FPSR
EBAT
FBAT
RESERVED
EPSR
FPSR
RESERVED
FPSM
PTI
Figure 33. Power Supply Management Interrupt Sources
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
RESERVED
ESAG
FSAG
FPSM
EPSM
Rev. B | Page 33 of 152
RESERVED
RESERVED
PSI
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM
interrupt (see Table 21). Figure 33 illustrates how the PSM
interrupt vector is shared among the PSM interrupt sources.
The PSM interrupt flags are latched and must be cleared by
writing to the IPSMF power management interrupt flag SFR,
Address 0xF8 (see Table 18).
EVADC*
FVADC*
EADE
TRUE?
PENDING PSM
INTERRUPT
EBAT*
FBAT*
ETI
EPSM
EBSO
FBSO
EVDCIN*
FVDCIN*
ESI
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