ade7566acpzf8-rl Analog Devices, Inc., ade7566acpzf8-rl Datasheet - Page 76
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ade7566acpzf8-rl
Manufacturer Part Number
ade7566acpzf8-rl
Description
Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADE7566ACPZF8-RL.pdf
(152 pages)
- Current page: 76 of 152
- Download datasheet (3Mb)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
If 0 is written to any of these registers, 1 is applied to the register.
The ratio of CFxNUM/CFxDEN should be less than 1 to ensure
proper operation. If the ratio of the CFxNUM/CFxDEN registers
is greater than 1, the register values are adjusted to a ratio of 1.
For example, if the output frequency is 1.562 kHz, and the
content of CFxDEN is 0 (0x000), the output frequency can be
set to 6.1 Hz by writing 0xFF to the CFxDEN register.
ENERGY REGISTER SCALING
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide measurements of active, reactive, and
apparent energies that use separate paths and filtering for
calculation. The difference in data paths can result in small
differences in LSB weight between active, reactive, and apparent
energy registers. These measurements are internally compensated
so that the scaling is nearly one to one. The relationship between
these registers is shown in Table 47.
Table 47. Energy Registers Scaling
Line Frequency = 50 Hz
Var = 0.9952 × Watt
VA = 0.9978 × Watt
Var = 0.9997 × Watt
VA = 0.9977 × Watt
Line Frequency = 60 Hz
Var = 0.9949 × Watt
VA = 1.0015 × Watt
Var = 0.9999 × Watt
VA = 1.0015 × Watt
Integrator
Off
Off
On
On
Rev. B | Page 76 of 152
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE7116/ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569 has its own interrupt
vector for the 8052 core, Vector Address 0x004B (see the
Interrupt Vectors section). The bits set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), Interrupt Enable 2 SFR
(MIRQENM, Address 0xDA), and Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) enable the energy measurement
interrupts that are allowed to interrupt the 8052 core. If an
event is not enabled, it cannot create a system interrupt.
The ADE interrupt stays active until the status bit that has created
the interrupt is cleared. The status bit is cleared when a 0 is
written to this register bit.
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