ade7566acpzf8-rl Analog Devices, Inc., ade7566acpzf8-rl Datasheet - Page 30
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ade7566acpzf8-rl
Manufacturer Part Number
ade7566acpzf8-rl
Description
Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADE7566ACPZF8-RL.pdf
(152 pages)
- Current page: 30 of 152
- Download datasheet (3Mb)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit
7
6
5
4
3
2
1
0
1
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit
[7:2]
[1:0]
Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit
7
6
5
4
3
2
[1:0]
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit
7
6
5
4
3
2
1
0
1
This feature is not available in the ADE7116.
This feature is not available in the ADE7116.
Bit Address
0xFF
0xFE
0xFD
0xFC
0xFB
0xFA
0xF9
0xF8
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
REF_BAT_EN
Reserved
RXPROG
Mnemonic
EPSR
Reserved
ESAG
Reserved
EVADC
EBAT
EBSO
EVDCIN
Mnemonic
Reserved
BATPRG
1
1
1
Mnemonic
FPSR
FPSM
FSAG
Reserved
FVADC
FBAT
FBSO
FVDCIN
Default
0
1
1
0
0
0
00
1
1
1
Default
00
00
Default
0
0
0
0
0
0
0
0
Description
If set, indicates that an Rx edge event triggered wake-up from PSM2.
Indicates the power supply that is internally connected to V
If set, indicates that V
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in
the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the
PLL_FLT bit.
Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in
PSM1 and PSM2 mode.
This bit must be kept at 0 for proper operation.
Controls the function of the P1.0/RxD pin.
RXPROG
00
01
11
Default
0
0
0
0
0
0
0
0
Description
Power supply restored interrupt flag. Set when the V
This occurs when the source of V
PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
This bit must be kept at 0 for proper operation.
VDCINADC monitor interrupt flag. Set when V
measurement is ready.
V
Battery switchover interrupt flag. Set when V
V
Description
These bits must be kept at 0 for proper operation.
Control bits for battery switchover.
BATPRG
00
01
1X
BAT
DCIN
monitor interrupt flag. Set when V
monitor interrupt flag. Set when V
Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
Reserved.
Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
This bit must be kept at 0 for proper operation.
Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.
Enables a PSM interrupt when the V
Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
Enables a PSM interrupt when the V
Description
Result
GPIO
RxD with wake-up disabled
RxD with wake-up enabled
DD
Rev. B | Page 30 of 152
power supply is ready for operation.
Result
Battery switchover enabled on low V
Battery switchover enabled on low V
Battery switchover disabled
SWOUT
BAT
changes from V
DCIN
falls below BATVTH or when V
BAT
DCIN
falls below 1.2 V.
monitor interrupt flag (FBAT) is set.
SWOUT
monitor interrupt flag (FVDCIN) is set.
DCIN
changes by VDCIN_DIFF or when V
switches from V
SWOUT
DD
BAT
DD
DD
power supply has been restored.
(0: V
to V
and low V
SWOUT
DD
.
= V
DD
DCIN
BAT
BAT
to V
; 1: V
measurement is ready.
BAT.
SWOUT
= V
DD
DCIN
).
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