ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 13
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ml67q5200
Manufacturer Part Number
ml67q5200
Description
Digital Audio Controller
Manufacturer
ETC-unknow
Datasheet
1.ML67Q5200.pdf
(28 pages)
External SDRAM Bus Timing
(V
1.
SDCKE output delay time
XA[19:1] output delay time
SDCS_N “L” output delay time
RAS_N “L” output delay time
RAS_N “H” output delay time
CAS_N “L” output delay time
CAS_N “H” output delay time
RAS/CAS minimum delay time
RAS active time
RAS precharge time
XWE_N “L” output delay time
XWE_N “H” output delay time
DQM[1]/DQM[0] “L” output delay time
DQM[1]/DQM[0] “H” output delay time
XD[15:0] input setup time
XD[15:0] input hold time
XD[15:0] output delay time
XD[15:0] output hold time
DD_CORE
nSD1 = t
t
RCD
, t
RAS
RCD
, and t
= 1.65 V to 1.95 V, V
, nSD2 = t
RP
Parameter
are parameters that can be set by the DRPC register. Refer to the User’s Manual for more information on these timings.
RAS
, nSD3 = t
RP
.
DD_IO
= 2.7 V to 3.6 V, T
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
[1]
SDCKED
SDXAD
SDCSLD
SDRASLD
SDRALHD
SDCASLD
SDCALHD
SDRCD
SDRAS
SDRP
SDWELD
SDWEHD
DOMD
DOMD
SDXDIS
SDXDIH
SDXDOD
SDXDOH
Symbol
A
= –30°C to +70°C)
Condition
CL = 50 pF
nSD1Tc
nSD2Tc
nSD3Tc
Min
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
15
-5
0
0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ML675200/ML67Q5200
Oki Semiconductor • 13
Max
10
10
10
10
10
10
10
—
—
—
10
10
10
10
—
—
10
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns