ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 8

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

ML675200/ML67Q5200
Pin Descriptions
1.
8
Classification
Oscillation
CPU JTAG
DSP JTAG
Power supply
Others
Connect all VDD_IO pins, all VDD_CORE pins, and all GND pins. If a device has one or more unconnected VDD_IO, VDD_CORE, or GND pins, proper device operation is not guaranteed.
• Oki Semiconductor
[1]
OSC0
OSC1_N
OSC2
OSC3_N
TCKA
TMSA
TRSTA_N
TDIA
TDOA
TCKT
TMST
TDIT
TINTP
TDOT
VDD_CORE
VDD_IO
VBUS
GND
TEST0
TEST1
TEST2
SDRAM-
MOD
Symbol
Type
VDD
VDD
VDD
GND
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Main clock oscillator input pin. Connect to a crystal or
ceramic oscillator of f = 8 MHz. When an external clock is
used, this pin is configured as the clock input.
Main clock oscillator output pin. Connect to a crystal or
ceramic oscillator of f = 8 MHz. The clock output is opposite
in phase to OSC0. Leave this pin unconnected when an exter-
nal clock is used.
Audio clock oscillator input pin. Connect to a crystal or
ceramic oscillator of f = 16.9344/ 11.2896 MHz. When an
external clock is used, this pin is configured as the clock
input.
Audio clock oscillator output pin. Connect to a crystal or
ceramic oscillator of f = 16.9344/ 11.2896 MHz. The clock
output is opposite in phase to OSC2. Leave this pin uncon-
nected when an external clock is used.
ARM JTAG clock input pin. Leave this pin unconnected for
normal operation.
ARM JTAG mode select input pin. Leave this pin unconnected
for normal operation.
ARM JTAG reset input pin. Leave this pin unconnected for
normal operation.
ARM JTAG data input pin. Leave this pin unconnected for
normal operation.
ARM JTAG data output pin. Leave this pin unconnected for
normal operation.
Teak-DSP JTAG clock input pin. Leave this pin unconnected
for normal operation.
Teak-DSP JTAG mode select input pin. Leave this pin uncon-
nected for normal operation.
Teak-DSP JTAG data input pin. Leave this pin unconnected for
normal operation.
Teak-DSP JAM interrupt output pin. Leave this pin uncon-
nected for normal operation.
Teak-DSP JTAG data output pin. Leave this pin unconnected
for normal operation.
Core power supply pin. Connect all the VDD_CORE pins.
IO power supply pin. Connect all the VDD_IO pins.
USB power supply pin (Vbus input pin).
CORE and I/O GND pin.
Test pin. Connect to GND pin for normal operation.
Test pin. Connect to VDD_IO pin for normal operation.
Test pin. Leave this pin unconnected for normal operation.
When this pin is “L” level, the NAND Flash memory interface
is enabled. When this pin is “H” level, the SDRAM interface
is enabled. This pin must not change state when power is
supplied.
Primary Function
Description
Symbol
Type
Secondary Function
Description