ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 22

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ml67q5200

Manufacturer Part Number
ml67q5200
Description
Digital Audio Controller
Manufacturer
ETC-unknow
Datasheet
ML675200/ML67Q5200
NAND Flash Interface
(V
1.
22
FWR_N pulse width
FWR_N “H” output hold time
Data (FD[7:0]) setup time
Data (FD[7:0]) hold time
FRD_N pulse width
FRD_N “H” output hold time
FRD_N access time
Data output hold time (FRD_N)
DD_CORE
Tc = HCLK cycle
To calculate, use the following w1, w2, and w3 values during sequencer write and the following r1 and r2 values during sequencer read:
w1: 0 for “no write wait” mode; 1 for “1 write wait” mode; 2 for “2 write wait” mode
w2: 1.5 for “no write wait” mode; 2 for “1 write wait” mode; 3 for “2 write wait” mode
w3: 0.5 for “no write wait” mode; 1 for “1 write wait” mode; 1 for “2 write wait” mode
r1: 1.5 for “no read wait” mode; 2 for “1 read wait” mode; 3 for “2 read wait” mode
r2: 0.5 for “no read wait” mode; 1 for “1 read wait” mode; 1 for “2 read wait” mode
• Oki Semiconductor
= 1.65 V to 1.95 V, V
Parameter
PIOE[7:0]/FD[7:0]
PIOE[7:0]/FD[7:0]
PIOE[9]/FWR_N
DD_IO
PIOE[8]/FRD_N
[1]
= 2.7 V to 3.6 V, TA = –30°C to +70°C)
t
t
t
t
t
t
t
t
FWP
FWH
FDS
FDH
FRP
FREH
FREA
FRHZ
Symbol
Condition
CL = 50 pF
Figure 13. Write Transfer
Figure 14. Read Transfer
t
FREA
t
t
FWP
FDS
t
FRP
t
t
FRHZ
FDH
t
(0.5·w1 + 1)Tc – 10
(0.5·w1 + 1)Tc – 10
FWH
t
FREH
w2·Tc – 20
w3·Tc – 10
r1·Tc – 10
r2·Tc – 10
r1·Tc – 20
Min.
0
t
FREA
t
t
FWP
FDS
t
t
FRHZ
FDH
(0.5·w1 + 1)Tc +10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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