ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 18

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

ML675200/ML67Q5200
Synchronous Serial Interface Timing
The synchronous serial interface operate in master mode or slave mode. It also
allows the user to set the polarity of the serial clock.
When the polarity of the serial clock is set to positive, as shown in the figure
below, transmit data (TXD) is driven on the falling edge of SIOCK. Receive
data is sampled on the rising edge of SIOCK. Once the transmission/reception
of the 8-bit data is completed, the clock stops at a high level, and the data
output holds the last data.
Master Mode
Slave Mode
18
Serial clock cycle
Output data delay time
Input data setup time
Input data hold time
Serial clock cycle
Output data delay time
Input data setup time
Input data hold time
• Oki Semiconductor
Parameter
Parameter
SIOCK
SIOCK
RXD
RXD
TXD
TXD
[1]
[1]
1. Indicates the case where the polarity of the serial clock is positive.
1. Indicates the case where the polarity of the serial clock is positive.
Figure 8. Synchronous Serial Interface – Master Mode Timing
Figure 9. Synchronous Serial Interface – Slave Mode Timing
T
t
t
t
T
t
t
t
MSSOD
MSSIS
MSSIH
SSSOD
SSSIS
SSSIH
Symbol
Symbol
t
t
MSSOD
SSSOD
t
t
MSSIS
SSSIS
Condition
C
Condition
C
L
L
= 50 pF
= 50 pF
When the polarity of the serial clock is set to negative, transmit data is driven
on the rising edge of SIOCK, and receive data is sampled on the falling edge
of SIOCK. Once the transmission/reception of 8-bit data is completed, the
clock stops at a low level, and the data output holds the last data.
T
T
t
t
MSSIH
SSSIH
66.67
66.67
Min
Min
—
40
—
20
20
0
VH = 2.0 V
VL = 0.8 V
VH = 2.0 V
VL = 0.8 V
Max
Max
—
20
—
—
—
—
—
40
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns