ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 19

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

I2C Bus Timing
1.
SCL clock frequency
SCL clock “L” period
SCL clock “H” period
Hold time (repetitive) “START” condition
(After this period, the first clock pulse is
generated.)
Setup time for repetitive “START” condition
Data hold time
Data setup time
Setup time for “STOP” condition
Although I2C bus devices in Fast mode can be used in a standard I2C bus system, it is necessary to satisfy the required condition t
signal.
If a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA pin at least “trmax + t
to the I2C Bus Specification) earlier than the time the SCL pin is opened
PIOE[13]/SDAT
PIOE[14]/SCL
Parameter
t
HD:S
t
f
t
t
t
t
t
t
t
LOW
SCL
LOW
HIGH
HD:STA
SU:STA
HD:DAT
SU:DAT
SU:STO
Symbol
t
HD:DAT
Figure 10. I2C Bus Timing
Min
250
t
4.7
4.0
4.0
4.7
5.0
4.0
SU:DAT
—
Standard Mode
t
HIGH
SU:DAT
SU:DAT
Max
100
= 1000 + 250 = 1250 ns” (output the data bits that are in effect in the Standard mode according
—
—
—
—
—
—
—
t
SU:STA
250 ns. This means that such devices do not automatically extend the “L” period of the SCL
t
HD:STA
100
Min
1.3
0.6
0.6
0.6
0.6
—
—
[1]
Fast Mode
Max
400
—
—
—
—
—
—
—
ML675200/ML67Q5200
Oki Semiconductor • 19
t
SU:STO
Units
kHz
µs
µs
µs
µs
µs
µs
µs