mc68hc908gp32 Freescale Semiconductor, Inc, mc68hc908gp32 Datasheet - Page 157
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mc68hc908gp32
Manufacturer Part Number
mc68hc908gp32
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GP32.pdf
(266 pages)
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Chapter 14
System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
Table 14-1
Freescale Semiconductor
•
•
•
Bus clock generation and control for CPU and peripherals:
–
–
Master reset control, including power-on reset (POR) and COP timeout
Interrupt arbitration
Stop/wait/reset/break entry and recovery
Internal clock control
Signal Name
shows the internal signal names used in this section.
CGMXCLK
CGMVCLK
CGMOUT
PORRST
IRST
R/W
IDB
IAB
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Table 14-1. Signal Name Conventions
MC68HC908GP32 Data Sheet, Rev. 10
Figure
Description
14-1.
Table 14-1
is a summary of the SIM
157
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